1+ -- This Source Code Form is subject to the terms of the Mozilla Public
2+ -- License, v. 2.0. If a copy of the MPL was not distributed with this
3+ -- file, You can obtain one at https://mozilla.org/MPL/2.0/.
4+ --
5+ -- Copyright 2025 Oxide Computer Company
6+
7+ library ieee;
8+ use ieee.std_logic_1164.all ;
9+ use ieee.numeric_std.all ;
10+ use work.axil8x32_pkg.all ;
11+
12+ -- Basic board support blocks including clock and reset generation
13+ -- board LEDs, and debugging I/O etc.
14+
15+ entity board_support is
16+ port (
17+ -- Board level clocks and resets
18+ board_50mhz_clk : in std_logic ;
19+ sp_fmc_clk : in std_logic ;
20+ sp_system_reset_l : in std_logic ;
21+ -- PLL outputs and synchronized resets
22+ clk_125m : out std_logic ;
23+ reset_125m : out std_logic ;
24+ clk_200m : out std_logic ;
25+ reset_200m : out std_logic ;
26+ reset_fmc : out std_logic ;
27+ -- misc board signals
28+ fpga1_status_led : out std_logic ;
29+ hubris_compat_ver : in std_logic_vector (2 downto 0 );
30+ -- AXI interface for the "info" block
31+ info_axi_if : view axil_target;
32+ ) ;
33+ end entity ;
34+
35+
36+ architecture rtl of board_support is
37+
38+ signal sp_system_reset_syncd : std_logic ;
39+ signal pll_locked_async : std_logic ;
40+ signal led_counter : unsigned (20 downto 0 );
41+
42+ begin
43+
44+ -- We have a reset pin coming in from the SP. Synchronize it first
45+ -- using the "raw" board clock, pre-PLL. We'll use this as the
46+ -- reset to the PLL, and the aclr the down-stream clocks
47+ clk50m_base_reset_sync : entity work .async_reset_bridge
48+ generic map (
49+ async_reset_active_level => '0'
50+ )
51+ port map (
52+ clk => board_50mhz_clk,
53+ reset_async => sp_system_reset_l,
54+ reset_sync => sp_system_reset_syncd -- polarity flip inside, now active high
55+ );
56+
57+ -- Xilinx PLL instantiation
58+ pll : entity work .cosmo_pll
59+ port map (
60+ clk_50m => board_50mhz_clk,
61+ clk_125m => clk_125m,
62+ clk_200m => clk_200m,
63+ reset => sp_system_reset_syncd,
64+ locked => pll_locked_async
65+
66+ );
67+
68+ -- Reset synchronizer into the clock domains
69+ reset_sync_inst : entity work .reset_sync
70+ port map (
71+ pll_locked_async => pll_locked_async,
72+ clk_125m => clk_125m,
73+ reset_125m => reset_125m,
74+ clk_200m => clk_200m,
75+ reset_200m => reset_200m,
76+ sp_fmc_clk => sp_fmc_clk,
77+ reset_fmc_clk => reset_fmc
78+ );
79+
80+ -- Blink an LED at some rate
81+ led : process (clk_125m, reset_125m)
82+ begin
83+ if reset_125m then
84+ led_counter <= (others => '0' );
85+ elsif rising_edge (clk_125m) then
86+ led_counter <= led_counter + 1 ;
87+ end if ;
88+ end process ;
89+ fpga1_status_led <= led_counter(20 );
90+
91+ -- Put the "info" common block here
92+ info_inst : entity work .info
93+ generic map (
94+ hubris_compat_num_bits => 3
95+ )
96+ port map (
97+ clk => clk_125m,
98+ reset => reset_125m,
99+ hubris_compat_pins => hubris_compat_ver,
100+ axi_if => info_axi_if
101+ );
102+
103+ end rtl ;
0 commit comments