GHDL doesn't strip asserts for synth

Author: nathanaelhuffman

hdl/ip/vhd/spi/axi_controller/spi_axi_pkg.vhd

@@ -70,7 +70,7 @@ package body spi_axi_pkg is
             when spi_opcode_bit_clr =>
                 return rdata and (not wdata);
             when others =>
-                assert false report "not a bit operation opcode" severity failure;
+                return rdata;
         end case;
 
     end function;

hdl/ip/vhd/spi/axi_controller/spi_axi_sms.vhd

@@ -215,8 +215,6 @@ begin
             v.state := OPCODE;
             v.opcode := (others => '0');
             v.req_addr := (others => '0');
-
-            -- TODO: any more clearing needed?
         end if;
 
         spi_rin <= v;

tools/yosys.bzl

@@ -65,7 +65,6 @@ def yosys_vhdl_synth(ctx):
     # depends on them. Buck2 is too smart such that since nothing depends
     # on them, it doesn't even build them 
     # This is a bit of a hack but it works for now.
-
     yosys_py = ctx.actions.declare_output("synth.py")
 
     yosys_gen = ctx.attrs._yosys_gen[RunInfo]

tools/yosys_gen/templates/synth_py.jinja2

@@ -22,7 +22,7 @@ cmd = [
     "-m",
     "ghdl",
     "-p",
-    f'ghdl --std=08 {files_str} -e {{project.top_entity_name}}; {{project.synth_family}} -json {args.output}',
+    f'ghdl --std=08 --no-formal {files_str} -e {{project.top_entity_name}}; {{project.synth_family}} -json {args.output}',
 ]
 
 a = subprocess.run(cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE, check=False)