Initial cosmo hp implementation

Author: nathanaelhuffman

hdl/projects/cosmo_hp/BUCK

@@ -4,6 +4,10 @@ load("//tools:yosys.bzl", "ice40_bitstream")
 vhdl_unit(
     name = "cosmo_hp_top",
     srcs = glob(["*.vhd"]),
+    deps = [
+        "//hdl/ip/vhd/synchronizers:async_reset_bridge",
+        "//hdl/ip/vhd/spi/axi_controller:spi_axi_controller",
+    ],
     standard = "2008",
 )
 

hdl/projects/cosmo_hp/cosmo_hp_top.vhd

@@ -2,10 +2,9 @@
 -- License, v. 2.0. If a copy of the MPL was not distributed with this
 -- file, You can obtain one at https://mozilla.org/MPL/2.0/.
 --
--- Copyright 2024 Oxide Computer Company
+-- Copyright 2025 Oxide Computer Company
 
 -- Cosmo Front Hot-plug FPGA targeting an ice40 HX8k
--- Pin names snapshot from 20Nov2024
 
 
 library ieee;
@@ -17,7 +16,6 @@ entity cosmo_hp_top is
     port (
         clk_50mhz_fpga2: in std_logic;
         sp_to_fpga2_system_reset_l: in std_logic;
-
         -- CEM A
         cema_to_fpga2_alert_l : in std_logic;
         cema_to_fpga2_ifdet_l : in std_logic;
@@ -137,7 +135,7 @@ entity cosmo_hp_top is
         -- MCIO I/F
         v12_mcio_a0hp_pg: in std_logic;
         fpga2_to_mcio_perst_l: out std_logic;
-        fpga2_to_mcio_prpe: out std_logic;
+        fpga2_to_mcio_prpe: in std_logic; -- TODO, confirm Hi-Z works with yosys + ghdl
         fpga2_to_v12_mcio_a0hp_hsc_en: out std_logic;
         -- FPGA1 I/F
         fpga1_to_fpga2_io: in std_logic_vector(5 downto 0); 
@@ -148,7 +146,7 @@ entity cosmo_hp_top is
         fpga2_to_sp_int_l: in std_logic_vector(2 downto 0); -- 3..1 in sch
         smbus_sp_to_fpga2_smclk: inout std_logic;
         smbus_sp_to_fpga2_smdat: inout std_logic;
-        spi_fpga2_to_sp_mux_dat: in std_logic;
+        spi_fpga2_to_sp_mux_dat: out std_logic;
         spi_sp_mux_to_fpga2_cs_l : in std_logic;
         spi_sp_mux_to_fpga2_dat : in std_logic;
         spi_sp_mux_to_fpga2_sck : in std_logic;
@@ -170,7 +168,71 @@ entity cosmo_hp_top is
 end entity;
 
 architecture rtl of cosmo_hp_top is
-
+    signal led_blink_cntr: unsigned(24 downto 0) := (others => '0');
+    signal reset_50m: std_logic;
 begin
 
+    -- Reset synchronizer
+    clk125m_sync: entity work.async_reset_bridge
+     generic map(
+        async_reset_active_level => '0'
+    )
+     port map(
+        clk => clk_50mhz_fpga2,
+        reset_async => sp_to_fpga2_system_reset_l,
+        reset_sync => reset_50m -- this is our synchronized reset now
+    );
+
+    -- Simple blinking LED based on a counter
+    led_blink: process(clk_50mhz_fpga2, reset_50m)
+    begin
+        if reset_50m then
+            led_blink_cntr <= (others => '0');
+        elsif rising_edge(clk_50mhz_fpga2) then
+            led_blink_cntr <= led_blink_cntr + 1;
+        end if;
+    end process;
+    fpga2_status_led <= led_blink_cntr(led_blink_cntr'high);
+
+    -- placeholder mcio stuff
+    fpga2_to_mcio_perst_l <= '0';
+    fpga2_to_v12_mcio_a0hp_hsc_en <= '0';
+
+    -- Our SPI target block
+    spi_axi_controller_inst: entity work.spi_axi_controller
+     port map(
+        clk => clk_50mhz_fpga2,
+        reset => reset_50m,
+        csn => spi_sp_mux_to_fpga2_cs_l,
+        sclk => spi_sp_mux_to_fpga2_sck,
+        copi => spi_sp_mux_to_fpga2_dat,
+        cipo => spi_fpga2_to_sp_mux_dat,
+        awvalid => open,
+        awready => '1',
+        awaddr => open,
+        wvalid => open,
+        wready => '1',
+        wdata => open,
+        wstrb => open,
+        bvalid => '1',
+        bready => open,
+        bresp => "00",
+        arvalid => open,
+        arready => '1',
+        araddr => open,
+        rvalid => '1',
+        rready => open,
+        rdata => (others => '0'),
+        rresp => "00"
+    );
+
+    -- Need AXI "fabric" block
+
+    -- Need Info block
+
+    -- Need qty 2 I/O expanders
+
+    -- Need qty 4 muxes
+
+
 end rtl;