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nathanaelhuffmannathanaelhuffman
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Initial structure for cosmo hotplug fpga
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‎hdl/projects/cosmo_hp/BUCK

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load("//tools:hdl.bzl", "vhdl_unit")
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load("//tools:yosys.bzl", "ice40_bitstream")
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vhdl_unit(
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name = "cosmo_hp_top",
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srcs = glob(["*.vhd"]),
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standard = "2008",
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)
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ice40_bitstream(
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name="cosmo_hp_bitstream",
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top_entity_name="cosmo_hp_top",
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top= ":cosmo_hp_top",
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family="hx8k",
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package="ct256",
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pinmap="cosmo_hp.pcf"
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)

‎hdl/projects/cosmo_hp/cosmo_hp.pcf

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set_io --warn-no-port cema_to_fpga2_alert_l F13
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set_io --warn-no-port cema_to_fpga2_ifdet_l F12
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set_io --warn-no-port cema_to_fpga2_pg_l C16
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set_io --warn-no-port cema_to_fpga2_prsnt_l G12
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set_io --warn-no-port cema_to_fpga2_pwrflt_l D16
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set_io --warn-no-port cema_to_fpga2_sharkfin_present F11
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set_io --warn-no-port cemb_to_fpga2_alert_l H16
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set_io --warn-no-port cemb_to_fpga2_ifdet_l J12
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set_io --warn-no-port cemb_to_fpga2_pg_l H11
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set_io --warn-no-port cemb_to_fpga2_prsnt_l K16
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set_io --warn-no-port cemb_to_fpga2_pwrflt_l K15
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set_io --warn-no-port cemb_to_fpga2_sharkfin_present J16
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set_io --warn-no-port cemc_to_fpga2_alert_l N16
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set_io --warn-no-port cemc_to_fpga2_ifdet_l P14
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set_io --warn-no-port cemc_to_fpga2_pg_l L12
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set_io --warn-no-port cemc_to_fpga2_prsnt_l R14
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set_io --warn-no-port cemc_to_fpga2_pwrflt_l P15
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set_io --warn-no-port cemc_to_fpga2_sharkfin_present M13
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set_io --warn-no-port cemd_to_fpga2_alert_l B4
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set_io --warn-no-port cemd_to_fpga2_ifdet_l A6
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set_io --warn-no-port cemd_to_fpga2_pg_l E6
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set_io --warn-no-port cemd_to_fpga2_prsnt_l D7
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set_io --warn-no-port cemd_to_fpga2_pwrflt_l B6
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set_io --warn-no-port cemd_to_fpga2_sharkfin_present A5
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set_io --warn-no-port ceme_to_fpga2_alert_l A11
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set_io --warn-no-port ceme_to_fpga2_ifdet_l B12
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set_io --warn-no-port ceme_to_fpga2_pg_l A10
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set_io --warn-no-port ceme_to_fpga2_prsnt_l D11
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set_io --warn-no-port ceme_to_fpga2_pwrflt_l E10
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set_io --warn-no-port ceme_to_fpga2_sharkfin_present B11
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set_io --warn-no-port cemf_to_fpga2_alert_l E16
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set_io --warn-no-port cemf_to_fpga2_ifdet_l G10
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set_io --warn-no-port cemf_to_fpga2_pg_l G14
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set_io --warn-no-port cemf_to_fpga2_prsnt_l H12
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set_io --warn-no-port cemf_to_fpga2_pwrflt_l G16
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set_io --warn-no-port cemf_to_fpga2_sharkfin_present G11
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set_io --warn-no-port cemg_to_fpga2_alert_l K14
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set_io --warn-no-port cemg_to_fpga2_ifdet_l J10
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set_io --warn-no-port cemg_to_fpga2_pg_l K13
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set_io --warn-no-port cemg_to_fpga2_prsnt_l K12
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set_io --warn-no-port cemg_to_fpga2_pwrflt_l L14
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set_io --warn-no-port cemg_to_fpga2_sharkfin_present J11
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set_io --warn-no-port cemh_to_fpga2_alert_l C3
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set_io --warn-no-port cemh_to_fpga2_ifdet_l C4
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set_io --warn-no-port cemh_to_fpga2_pg_l D3
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set_io --warn-no-port cemh_to_fpga2_prsnt_l C5
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set_io --warn-no-port cemh_to_fpga2_pwrflt_l D5
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set_io --warn-no-port cemh_to_fpga2_sharkfin_present D4
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set_io --warn-no-port cemi_to_fpga2_alert_l C7
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set_io --warn-no-port cemi_to_fpga2_ifdet_l A9
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set_io --warn-no-port cemi_to_fpga2_pg_l A7
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set_io --warn-no-port cemi_to_fpga2_prsnt_l D9
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set_io --warn-no-port cemi_to_fpga2_pwrflt_l C9
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set_io --warn-no-port cemi_to_fpga2_sharkfin_present D8
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set_io --warn-no-port cemj_to_fpga2_alert_l A15
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set_io --warn-no-port cemj_to_fpga2_ifdet_l B14
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set_io --warn-no-port cemj_to_fpga2_pg_l A16
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set_io --warn-no-port cemj_to_fpga2_prsnt_l D13
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set_io --warn-no-port cemj_to_fpga2_pwrflt_l C14
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set_io --warn-no-port cemj_to_fpga2_sharkfin_present E11
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set_io --warn-no-port clk_50mhz_fpga2 F7
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set_io --warn-no-port clk_buff_cemabcd_to_fpga2_los_l K9
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set_io --warn-no-port clk_buff_cemefg_to_fpga2_los_l N12
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set_io --warn-no-port clk_buff_cemhij_to_fpga2_los_l T10
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set_io --warn-no-port fpga1_to_fpga2_io[0] D1
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set_io --warn-no-port fpga1_to_fpga2_io[1] G4
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set_io --warn-no-port fpga1_to_fpga2_io[2] E3
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set_io --warn-no-port fpga1_to_fpga2_io[3] H5
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set_io --warn-no-port fpga1_to_fpga2_io[4] E2
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set_io --warn-no-port fpga1_to_fpga2_io[5] G3
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set_io --warn-no-port fpga2_spare_v3p3[0] E4
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set_io --warn-no-port fpga2_spare_v3p3[1] B2
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set_io --warn-no-port fpga2_spare_v3p3[2] F5
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set_io --warn-no-port fpga2_spare_v3p3[3] B1
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set_io --warn-no-port fpga2_spare_v3p3[4] C1
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set_io --warn-no-port fpga2_spare_v3p3[5] C2
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set_io --warn-no-port fpga2_spare_v3p3[6] F4
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set_io --warn-no-port fpga2_spare_v3p3[7] D2
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set_io --warn-no-port fpga2_status_led B9
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set_io --warn-no-port fpga2_to_cema_attnled R4
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set_io --warn-no-port fpga2_to_cema_perst_l F14
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set_io --warn-no-port fpga2_to_cema_pwren E14
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set_io --warn-no-port fpga2_to_cemb_attnled T3
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set_io --warn-no-port fpga2_to_cemb_perst_l J14
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set_io --warn-no-port fpga2_to_cemb_pwren H13
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set_io --warn-no-port fpga2_to_cemc_attnled R3
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set_io --warn-no-port fpga2_to_cemc_perst_l R15
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set_io --warn-no-port fpga2_to_cemc_pwren M14
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set_io --warn-no-port fpga2_to_cemd_attnled T2
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set_io --warn-no-port fpga2_to_cemd_perst_l C6
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set_io --warn-no-port fpga2_to_cemd_pwren B5
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set_io --warn-no-port fpga2_to_ceme_attnled R2
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set_io --warn-no-port fpga2_to_ceme_perst_l C11
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set_io --warn-no-port fpga2_to_ceme_pwren C10
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set_io --warn-no-port fpga2_to_cemf_attnled R5
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set_io --warn-no-port fpga2_to_cemf_perst_l G15
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set_io --warn-no-port fpga2_to_cemf_pwren F15
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set_io --warn-no-port fpga2_to_cemg_attnled P4
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set_io --warn-no-port fpga2_to_cemg_perst_l M16
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set_io --warn-no-port fpga2_to_cemg_pwren L16
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set_io --warn-no-port fpga2_to_cemh_attnled P5
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set_io --warn-no-port fpga2_to_cemh_perst_l A1
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set_io --warn-no-port fpga2_to_cemh_pwren E5
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set_io --warn-no-port fpga2_to_cemi_attnled N5
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set_io --warn-no-port fpga2_to_cemi_perst_l E9
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set_io --warn-no-port fpga2_to_cemi_pwren B8
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set_io --warn-no-port fpga2_to_cemj_attnled M7
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set_io --warn-no-port fpga2_to_cemj_perst_l B15
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set_io --warn-no-port fpga2_to_cemj_pwren C13
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set_io --warn-no-port fpga2_to_clk_buff_cema_oe_l N9
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set_io --warn-no-port fpga2_to_clk_buff_cemb_oe_l T9
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set_io --warn-no-port fpga2_to_clk_buff_cemc_oe_l M9
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set_io --warn-no-port fpga2_to_clk_buff_cemd_oe_l R9
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set_io --warn-no-port fpga2_to_clk_buff_ceme_oe_l T15
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set_io --warn-no-port fpga2_to_clk_buff_cemf_oe_l T14
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set_io --warn-no-port fpga2_to_clk_buff_cemg_oe_l M11
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set_io --warn-no-port fpga2_to_clk_buff_cemh_oe_l R10
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set_io --warn-no-port fpga2_to_clk_buff_cemi_oe_l L10
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set_io --warn-no-port fpga2_to_clk_buff_cemj_oe_l P10
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set_io --warn-no-port fpga2_to_clk_buff_mcio_oe_l T13
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set_io --warn-no-port fpga2_to_clk_buff_ufl_oe_l N10
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set_io --warn-no-port fpga2_to_i2c_mux4_sel[0] K1
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set_io --warn-no-port fpga2_to_i2c_mux4_sel[1] J1
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set_io --warn-no-port fpga2_to_i2c_mux5_sel[0] L1
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set_io --warn-no-port fpga2_to_i2c_mux5_sel[1] M1
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set_io --warn-no-port fpga2_to_i2c_mux6_sel[0] M3
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set_io --warn-no-port fpga2_to_i2c_mux6_sel[1] L5
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set_io --warn-no-port fpga2_to_i2c_mux7_sel[0] H2
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set_io --warn-no-port fpga2_to_i2c_mux7_sel[1] G2
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set_io --warn-no-port fpga2_to_i2c_mux8_sel[0] F1
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set_io --warn-no-port fpga2_to_i2c_mux8_sel[1] G1
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set_io --warn-no-port fpga2_to_mcio_perst_l J3
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set_io --warn-no-port fpga2_to_mcio_prpe H1
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set_io --warn-no-port fpga2_to_sp_int_l[0] M4
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set_io --warn-no-port fpga2_to_sp_int_l[1] P2
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set_io --warn-no-port fpga2_to_sp_int_l[2] M5
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set_io --warn-no-port fpga2_to_v12_mcio_a0hp_hsc_en F2
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set_io --warn-no-port i2c_sp5_to_fpga2_scl M2
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set_io --warn-no-port i2c_sp5_to_fpga2_sda L7
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set_io --warn-no-port i2c_sp5_to_fpga2_xltr_en N2
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set_io --warn-no-port smbus_sp_to_fpga2_smclk T7
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set_io --warn-no-port smbus_sp_to_fpga2_smdat T8
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set_io --warn-no-port sp5_to_fpga_genint_3v3_l K5
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set_io --warn-no-port sp_to_fpga2_system_reset_l N6
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set_io --warn-no-port spi_fpga2_to_sp_mux_dat P12
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set_io --warn-no-port spi_sp_mux_to_fpga2_cs_l R12
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set_io --warn-no-port spi_sp_mux_to_fpga2_dat P11
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set_io --warn-no-port spi_sp_mux_to_fpga2_sck R11
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set_io --warn-no-port uart_fpga2_to_sp_dat N4
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set_io --warn-no-port uart_sp_to_fpga2_dat R1
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set_io --warn-no-port v12_mcio_a0hp_pg H6

‎hdl/projects/cosmo_hp/cosmo_hp_top.vhd

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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
4+
--
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-- Copyright 2024 Oxide Computer Company
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-- Cosmo Front Hot-plug FPGA targeting an ice40 HX8k
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-- Pin names snapshot from 20Nov2024
9+
10+
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library ieee;
12+
use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
14+
use ieee.numeric_std_unsigned.all;
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entity cosmo_hp_top is
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port (
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clk_50mhz_fpga2: in std_logic;
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sp_to_fpga2_system_reset_l: in std_logic;
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-- CEM A
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cema_to_fpga2_alert_l : in std_logic;
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cema_to_fpga2_ifdet_l : in std_logic;
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cema_to_fpga2_pg_l : in std_logic;
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cema_to_fpga2_prsnt_l : in std_logic;
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cema_to_fpga2_pwrflt_l : in std_logic;
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cema_to_fpga2_sharkfin_present : in std_logic;
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fpga2_to_cema_attnled: out std_logic;
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fpga2_to_cema_perst_l : out std_logic;
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fpga2_to_cema_pwren : out std_logic;
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-- CEM B
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cemb_to_fpga2_alert_l : in std_logic;
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cemb_to_fpga2_ifdet_l : in std_logic;
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cemb_to_fpga2_pg_l : in std_logic;
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cemb_to_fpga2_prsnt_l : in std_logic;
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cemb_to_fpga2_pwrflt_l : in std_logic;
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cemb_to_fpga2_sharkfin_present : in std_logic;
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fpga2_to_cemb_attnled: out std_logic;
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fpga2_to_cemb_perst_l : out std_logic;
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fpga2_to_cemb_pwren : out std_logic;
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-- CEM C
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cemc_to_fpga2_alert_l : in std_logic;
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cemc_to_fpga2_ifdet_l : in std_logic;
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cemc_to_fpga2_pg_l : in std_logic;
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cemc_to_fpga2_prsnt_l : in std_logic;
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cemc_to_fpga2_pwrflt_l : in std_logic;
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cemc_to_fpga2_sharkfin_present : in std_logic;
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fpga2_to_cemc_attnled: out std_logic;
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fpga2_to_cemc_perst_l : out std_logic;
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fpga2_to_cemc_pwren : out std_logic;
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-- CEM D
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cemd_to_fpga2_alert_l: in std_logic;
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cemd_to_fpga2_ifdet_l: in std_logic;
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cemd_to_fpga2_pg_l: in std_logic;
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cemd_to_fpga2_prsnt_l: in std_logic;
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cemd_to_fpga2_pwrflt_l: in std_logic;
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cemd_to_fpga2_sharkfin_present: in std_logic;
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fpga2_to_cemd_attnled: out std_logic;
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fpga2_to_cemd_perst_l: out std_logic;
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fpga2_to_cemd_pwren: out std_logic;
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-- CEM E
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ceme_to_fpga2_alert_l : in std_logic;
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ceme_to_fpga2_ifdet_l : in std_logic;
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ceme_to_fpga2_pg_l : in std_logic;
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ceme_to_fpga2_prsnt_l : in std_logic;
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ceme_to_fpga2_pwrflt_l : in std_logic;
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ceme_to_fpga2_sharkfin_present : in std_logic;
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fpga2_to_ceme_attnled: out std_logic;
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fpga2_to_ceme_perst_l : out std_logic;
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fpga2_to_ceme_pwren : out std_logic;
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-- CEM F
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cemf_to_fpga2_alert_l : in std_logic;
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cemf_to_fpga2_ifdet_l : in std_logic;
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cemf_to_fpga2_pg_l : in std_logic;
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cemf_to_fpga2_prsnt_l : in std_logic;
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cemf_to_fpga2_pwrflt_l : in std_logic;
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cemf_to_fpga2_sharkfin_present : in std_logic;
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fpga2_to_cemf_attnled: out std_logic;
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fpga2_to_cemf_perst_l : out std_logic;
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fpga2_to_cemf_pwren : out std_logic;
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-- CEM G
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cemg_to_fpga2_alert_l : in std_logic;
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cemg_to_fpga2_ifdet_l : in std_logic;
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cemg_to_fpga2_pg_l : in std_logic;
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cemg_to_fpga2_prsnt_l : in std_logic;
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cemg_to_fpga2_pwrflt_l : in std_logic;
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cemg_to_fpga2_sharkfin_present : in std_logic;
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fpga2_to_cemg_attnled: out std_logic;
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fpga2_to_cemg_perst_l : out std_logic;
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fpga2_to_cemg_pwren : out std_logic;
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-- CEM H
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cemh_to_fpga2_alert_l: in std_logic;
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cemh_to_fpga2_ifdet_l: in std_logic;
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cemh_to_fpga2_pg_l: in std_logic;
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cemh_to_fpga2_prsnt_l: in std_logic;
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cemh_to_fpga2_pwrflt_l: in std_logic;
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cemh_to_fpga2_sharkfin_present: in std_logic;
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fpga2_to_cemh_attnled: out std_logic;
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fpga2_to_cemh_perst_l: out std_logic;
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fpga2_to_cemh_pwren: out std_logic;
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-- CEM I
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cemi_to_fpga2_alert_l: in std_logic;
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cemi_to_fpga2_ifdet_l: in std_logic;
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cemi_to_fpga2_pg_l: in std_logic;
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cemi_to_fpga2_prsnt_l: in std_logic;
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cemi_to_fpga2_pwrflt_l: in std_logic;
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cemi_to_fpga2_sharkfin_present: in std_logic;
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fpga2_to_cemi_attnled: out std_logic;
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fpga2_to_cemi_perst_l: out std_logic;
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fpga2_to_cemi_pwren: out std_logic;
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-- CEM J
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cemj_to_fpga2_alert_l : in std_logic;
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cemj_to_fpga2_ifdet_l : in std_logic;
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cemj_to_fpga2_pg_l : in std_logic;
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cemj_to_fpga2_prsnt_l : in std_logic;
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cemj_to_fpga2_pwrflt_l : in std_logic;
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cemj_to_fpga2_sharkfin_present : in std_logic;
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fpga2_to_cemj_attnled: out std_logic;
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fpga2_to_cemj_perst_l : out std_logic;
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fpga2_to_cemj_pwren : out std_logic;
121+
-- CLK Buffer I/F
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clk_buff_cemabcd_to_fpga2_los_l: in std_logic;
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clk_buff_cemefg_to_fpga2_los_l : in std_logic;
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clk_buff_cemhij_to_fpga2_los_l : in std_logic;
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fpga2_to_clk_buff_cema_oe_l: out std_logic;
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fpga2_to_clk_buff_cemb_oe_l: out std_logic;
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fpga2_to_clk_buff_cemc_oe_l: out std_logic;
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fpga2_to_clk_buff_cemd_oe_l: out std_logic;
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fpga2_to_clk_buff_ceme_oe_l : out std_logic;
130+
fpga2_to_clk_buff_cemf_oe_l : out std_logic;
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fpga2_to_clk_buff_cemg_oe_l : out std_logic;
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fpga2_to_clk_buff_cemh_oe_l : out std_logic;
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fpga2_to_clk_buff_cemi_oe_l : out std_logic;
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fpga2_to_clk_buff_cemj_oe_l : out std_logic;
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fpga2_to_clk_buff_mcio_oe_l : out std_logic;
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fpga2_to_clk_buff_ufl_oe_l : out std_logic;
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-- MCIO I/F
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v12_mcio_a0hp_pg: in std_logic;
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fpga2_to_mcio_perst_l: out std_logic;
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fpga2_to_mcio_prpe: out std_logic;
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fpga2_to_v12_mcio_a0hp_hsc_en: out std_logic;
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-- FPGA1 I/F
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fpga1_to_fpga2_io: in std_logic_vector(5 downto 0);
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-- FPGA misc I/O
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fpga2_spare_v3p3: in std_logic_vector(7 downto 0);
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fpga2_status_led: out std_logic;
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-- SP I/F
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fpga2_to_sp_int_l: in std_logic_vector(2 downto 0); -- 3..1 in sch
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smbus_sp_to_fpga2_smclk: inout std_logic;
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smbus_sp_to_fpga2_smdat: inout std_logic;
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spi_fpga2_to_sp_mux_dat: in std_logic;
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spi_sp_mux_to_fpga2_cs_l : in std_logic;
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spi_sp_mux_to_fpga2_dat : in std_logic;
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spi_sp_mux_to_fpga2_sck : in std_logic;
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uart_fpga2_to_sp_dat: in std_logic;
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uart_sp_to_fpga2_dat: in std_logic;
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-- I2C Muxes
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fpga2_to_i2c_mux4_sel: in std_logic_vector(1 downto 0);
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fpga2_to_i2c_mux5_sel: in std_logic_vector(1 downto 0);
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fpga2_to_i2c_mux6_sel: in std_logic_vector(1 downto 0);
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fpga2_to_i2c_mux7_sel: in std_logic_vector(1 downto 0);
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fpga2_to_i2c_mux8_sel: in std_logic_vector(1 downto 0);
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-- SP5 I/F
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i2c_sp5_to_fpga2_scl: inout std_logic;
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i2c_sp5_to_fpga2_sda: inout std_logic;
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i2c_sp5_to_fpga2_xltr_en: in std_logic;
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sp5_to_fpga_genint_3v3_l: in std_logic
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);
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end entity;
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architecture rtl of cosmo_hp_top is
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174+
begin
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176+
end rtl;

‎tools/yosys.bzl

+6
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@ def ice40_nextpnr(ctx, yoys_providers):
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asc = ctx.actions.declare_output("{}.asc".format(ctx.attrs.name))
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cmd = cmd_args()
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cmd.add(ctx.attrs._nextpnr_ice40[RunInfo])
76+
cmd.add(next_pnr_family_flags(ctx.attrs.family))
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cmd.add("--package", ctx.attrs.package)
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cmd.add("--pcf", ctx.attrs.pinmap)
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cmd.add("--json", yosys_json)
@@ -83,6 +84,10 @@ def ice40_nextpnr(ctx, yoys_providers):
8384
providers.append(DefaultInfo(default_output=asc))
8485
return providers
8586

87+
# naive implemenation of turning family into nextpnr flags
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def next_pnr_family_flags(family):
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return "--{}".format(family)
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8691

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def icepack(ctx, next_pnr_providers):
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providers = []
@@ -104,6 +109,7 @@ ice40_bitstream = rule(
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attrs={
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"top_entity_name": attrs.string(),
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"top": attrs.dep(doc="Expected top HDL unit"),
112+
"family": attrs.string(doc="FPGA family"),
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"package": attrs.string(doc="Supported FPGA package"),
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"pinmap": attrs.source(doc="Pin constraints file *.pcf"),
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"_yosys_gen": attrs.exec_dep(

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