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fix, needs polishing
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3 files changed

+57
-12
lines changed

3 files changed

+57
-12
lines changed

hdl/ip/bsv/I2C/I2CBitController.bsv

+3-3
Original file line numberDiff line numberDiff line change
@@ -155,14 +155,14 @@ module mkI2CBitController #(
155155
// After the delay we know SCL is being stretched if we aren't the ones
156156
// holding it low.
157157
(* fire_when_enabled *)
158-
rule do_sample_scl_stretch(scl_stretch_sample_strobe && scl_in == 0 && state != AwaitStart);
159-
scl_stretching <= scl_out_en == 0;
158+
rule do_sample_scl_stretch(scl_stretch_sample_strobe);
159+
scl_stretching <= scl_out_en == 0 && scl_in == 0;
160160
scl_stretch_sample_delay <= False;
161161
endrule
162162

163163
// If SCL is high then no one is holding it
164164
(* fire_when_enabled *)
165-
rule do_clear_scl_stretch(scl_in == 1 || state == AwaitStart);
165+
rule do_clear_scl_stretch(scl_in == 1 && !scl_stretch_sample_strobe);
166166
scl_stretching <= False;
167167
endrule
168168

hdl/projects/sidecar/qsfp_x32/QSFPModule/test/QsfpModuleControllerTests.bsv

+42-2
Original file line numberDiff line numberDiff line change
@@ -130,9 +130,9 @@ module mkBench (Bench);
130130

131131
// Connect I2C busses since TriStates cannot be simulated
132132
mkConnection(controller.pins.scl.out, periph.scl_i);
133-
mkConnection(controller.pins.scl.in, periph.scl_o);
133+
mkConnection(periph.scl_o, controller.pins.scl.in);
134134
mkConnection(controller.pins.sda.out, periph.sda_i);
135-
mkConnection(controller.pins.sda.in, periph.sda_o);
135+
mkConnection(periph.sda_o, controller.pins.sda.in);
136136

137137
// We need the ability to simulate the bus losing its pull-ups when a module has not been
138138
// inserted since that is how the design behaves. We only apply power to the module (and by the
@@ -745,4 +745,44 @@ module mkI2CSclStretchTimeoutTest (Empty);
745745
endseq);
746746
endmodule
747747

748+
// mkUninitializationAfterRemovalTest
749+
//
750+
// This test ensures that a previously initialized module is uninitialized when
751+
// the module is removed regardless of `ResetL`'s status. That way when it is
752+
// reinserted, the initialization process happens again.
753+
module mkSclStretchTimeoutAfterRemovalAndReinsertionTest (Empty);
754+
Bench bench <- mkBench();
755+
756+
Command read_cmd = Command {
757+
op: Read,
758+
i2c_addr: i2c_test_params.peripheral_addr,
759+
reg_addr: 8'h00,
760+
num_bytes: 1
761+
};
762+
763+
mkAutoFSM(seq
764+
add_and_initialize_module(bench);
765+
bench.command(read_cmd, False, False);
766+
await(!bench.i2c_busy());
767+
assert_eq(unpack(bench.registers.port_status.error[2:0]),
768+
NoError,
769+
"NoError should be present when attempting to communicate after t_init has elapsed.");
770+
771+
remove_and_power_down_module(bench);
772+
773+
774+
insert_and_power_module(bench);
775+
776+
bench.command(read_cmd, False, False);
777+
await(!bench.i2c_busy());
778+
delay(3);
779+
assert_eq(unpack(bench.registers.port_status.error[2:0]),
780+
NotInitialized,
781+
"NotInitialized error should be present when a module has been reseated but not initialized.");
782+
assert_eq(unpack(bench.registers.port_status.stretching_seen),
783+
False,
784+
"Should not have observed and SCL stretching.");
785+
endseq);
786+
endmodule
787+
748788
endpackage: QsfpModuleControllerTests

hdl/projects/sidecar/qsfp_x32/QSFPModule/test/QsfpModuleControllerTests.gtkw

+12-7
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,19 @@
11
[*]
22
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
3-
[*] Thu Dec 5 13:08:47 2024
3+
[*] Thu Dec 5 20:23:37 2024
44
[*]
55
[dumpfile] "/home/aaron/Oxide/git/quartz/build/vcd/QsfpModuleControllerTests_mkUninitializationAfterRemovalTest.vcd"
6-
[dumpfile_mtime] "Thu Dec 5 13:00:44 2024"
6+
[dumpfile_mtime] "Thu Dec 5 19:45:50 2024"
77
[dumpfile_size] 93767403
88
[savefile] "/home/aaron/Oxide/git/quartz/hdl/projects/sidecar/qsfp_x32/QSFPModule/test/QsfpModuleControllerTests.gtkw"
9-
[timestart] 13499672
9+
[timestart] 8598640
1010
[size] 2592 1283
1111
[pos] -1 -1
12-
*-7.171101 13500140 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
12+
*-11.242826 8530010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
1313
[treeopen] main.
1414
[treeopen] main.top.
15-
[sst_width] 596
16-
[signals_width] 645
15+
[sst_width] 445
16+
[signals_width] 603
1717
[sst_expanded] 1
1818
[sst_vpaned_height] 404
1919
@200
@@ -28,6 +28,7 @@ main.top.bench_modprsl_r
2828
@28
2929
main.top.bench_controller_hot_swap_enabled_r
3030
main.top.bench_hsc_pg_r
31+
main.top.bench_controller_power_good__output_r
3132
@200
3233
-
3334
-State
@@ -50,8 +51,12 @@ main.top.bench_controller_wdata_fifo_deq
5051
-
5152
-I2CCore
5253
@28
54+
main.top.bench_controller_i2c_core_bit_ctrl_sda_out_en
55+
main.top.bench_controller_i2c_core_bit_ctrl_scl_out_en
5356
main.top.bench_controller_i2c_core_bit_ctrl_sda_in
5457
main.top.bench_controller_i2c_core_bit_ctrl_scl_in
58+
@25
59+
main.top.bench_controller_i2c_core_bit_ctrl_state[2:0]
5560
@22
5661
main.top.bench_controller_i2c_core_state_r[3:0]
5762
@28
@@ -66,7 +71,7 @@ main.top.bench_periph_scl_stretch_countdown_q
6671
main.top.bench_controller_i2c_core_bit_ctrl_scl_stretch_timeout_cntr_count[15:0]
6772
@28
6873
main.top.bench_controller_i2c_core_bit_ctrl_scl_stretch_timeout_cntr_q
69-
@25
74+
@24
7075
main.top.bench_controller_i2c_core_bit_ctrl_scl_stretch_sample_strobe_count[5:0]
7176
@28
7277
main.top.bench_controller_i2c_core_bit_ctrl_scl_stretch_sample_strobe_q

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