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nathanaelhuffmannathanaelhuffman
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SPI<->AXI interface
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‎hdl/ip/vhd/spi/axi_controller/BUCK

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load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
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load("//tools:rdl.bzl", "rdl_file")
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vhdl_unit(
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name = "spi_axi_controller",
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srcs = glob(["*.vhd",]),
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deps = [
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"//hdl/ip/vhd/spi/spi_target_phy:spi_target_phy",
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],
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visibility = ['PUBLIC']
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)
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vunit_sim(
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name = "spi_axi_tb",
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srcs = glob(["sims/**/*.vhd"]),
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deps = [
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":spi_axi_controller",
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"//hdl/ip/vhd/vunit_components:spi_vcs",
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"//hdl/ip/vhd/i2c/target:i2c_phy_consolidator",
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],
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visibility = ['PUBLIC'],
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)

‎hdl/ip/vhd/spi/axi_controller/docs/README.adoc

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It supports Mode 0 (0,0) and mode3 (1,1) transfers. It is expected that there are fewer than 256 addressable registers, but we’re picking 16bit addressing for future extensibility without changing the protocol and to support a circular buffer for storing event history.
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SPI instructions
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[cols=4,options="header"]
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|===
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|Opcode| Instruction Name | Description| Notes
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| 0x0 | Write byte(s) | Write one or more contiguous bytes |
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| 0x1| Read byte(s) | Read one or more contiguous bytes|
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| 0x2| Bit set | hardware does a bit-wise OR with data and current register state | new_reg = old_reg \|\| data
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| 0x3| Bit clr | hardware does a bit-wise clear with data and current register state |new_reg = old_reg && !data
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|===
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Note that for the bit-set and bit-clear spi instructions, the AXI controller internally does a read-modify-write operation, resulting
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in a read of the current register state, a bitwise operation with the data, and a write back of the new register state. These are
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not good operations to use if the registers you're modifiying have read-side effects.

‎hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb.vhd

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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
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--
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-- Copyright 2024 Oxide Computer Company
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std_unsigned.all;
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library vunit_lib;
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context vunit_lib.com_context;
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context vunit_lib.vunit_context;
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context vunit_lib.vc_context;
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use vunit_lib.spi_pkg.all;
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use work.spi_axi_tb_pkg.all;
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use work.spi_axi_pkg.all;
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entity spi_axi_tb is
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generic (
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runner_cfg : string
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);
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end entity;
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architecture tb of spi_axi_tb is
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begin
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th: entity work.spi_axi_th;
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bench: process
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alias reset is << signal th.reset : std_logic >>;
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alias csn is << signal th.csn : std_logic >>;
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variable buf : buffer_t;
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variable buf2 : buffer_t;
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variable data : std_logic_vector(7 downto 0) := (others => '0');
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variable expected_data : std_logic_vector(7 downto 0) := (others => '0');
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variable address : std_logic_vector(15 downto 0) := (others => '0');
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variable tx_queue : queue_t := new_queue;
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begin
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-- Always the first thing in the process, set up things for the VUnit test runner
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test_runner_setup(runner, runner_cfg);
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show_all(wr_logger, display_handler);
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-- Reach into the test harness, which generates and de-asserts reset and hold the
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-- test cases off until we're out of reset. This runs for every test case
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wait until reset = '0';
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wait for 500 ns; -- let the resets propagate
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while test_suite loop
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if run("single-read") then
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-- set up the "memory to be read with a known value"
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buf := allocate(rmemory, 1 * 64, alignment => 32);
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-- Use the simulation interface to set the data we're going to read back
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expected_data := X"AA";
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write_word(rmemory, 0, expected_data);
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-- TB will fault if DUT tries to write to this memory
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set_permissions(rmemory, 0, read_only);
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-- issue spi read command (data is dummy byte here since this is a)
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spi_send_byte(net, spi_opcode_read, address, (others => '0'), csn);
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-- Read back word rx'd from DUT and check it matches expected.
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-- -- we're going to have 3 dummy bytes here, skip them, keeping the 4th
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for i in 0 to 3 loop
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pop_stream(net, master_rstream, data);
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end loop;
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check_equal(data, expected_data, "Read data did not match expected");
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elsif run("single-write") then
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-- set up the "memory to be read with a known value"
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buf := allocate(wmemory, 1 * 64, alignment => 32);
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-- Use the simulation interface to set the data we're expected to write
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expected_data := X"AA";
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set_expected_word(wmemory, 0, expected_data);
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-- issue spi write command
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spi_send_byte(net, spi_opcode_write, address, expected_data, csn);
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-- no reach into the ram and see what is there now
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wait for 20 ns;
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check_expected_was_written(buf);
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elsif run("single-bit-set") then
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-- Due to how the axi blocks by vunit work, we need to set up 2 buffers, one for the
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-- read side and one for the write-side
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-- READ SIDE is buf
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-- set up the "memory to be read with a known value"
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buf := allocate(rmemory, 1 * 64, alignment => 32);
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-- WRITE SIDE is buf2
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buf2 := allocate(wmemory, 1 * 64, alignment => 32);
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-- Sick X"AA" into the read buffer, this is going to be our starting point for the bit-set
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-- Use the simulation interface to set the data we're going to read back
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expected_data := X"AA";
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write_word(rmemory, 0, expected_data);
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-- Our Write address now has X"AA" in it.
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data := X"05";
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-- This is the expected write into the write-side after the read-modify-write bit-set operation
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expected_data := expected_data or data;
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set_expected_word(wmemory, 0, expected_data);
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-- issue spi write command for bit set with data bits
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spi_send_byte(net, spi_opcode_bit_set, address, data, csn);
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-- no reach into the ram and see what is there now
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wait for 1 us;
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check_expected_was_written(buf2);
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elsif run("single-bit-clr") then
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-- Due to how the axi blocks by vunit work, we need to set up 2 buffers, one for the
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-- read side and one for the write-side
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-- READ SIDE is buf
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-- set up the "memory to be read with a known value"
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buf := allocate(rmemory, 1 * 64, alignment => 32);
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-- WRITE SIDE is buf2
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buf2 := allocate(wmemory, 1 * 64, alignment => 32);
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-- Sick X"AA" into the read buffer, this is going to be our starting point for the bit-set
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-- Use the simulation interface to set the data we're going to read back
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expected_data := X"AA";
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write_word(rmemory, 0, expected_data);
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-- Our Write address now has X"AA" in it.
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data := X"0A";
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-- This is the expected write into the write-side after the read-modify-write bit-set operation
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expected_data := expected_data and (not data);
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set_expected_word(wmemory, 0, expected_data);
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-- issue spi write command for bit set with data bits
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spi_send_byte(net, spi_opcode_bit_clr, address, data, csn);
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-- no reach into the ram and see what is there now
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wait for 20 ns;
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check_expected_was_written(buf2);
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elsif run("multi-read") then
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-- set up the "memory to be read with a known value"
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buf := allocate(rmemory, 4 * 32, alignment => 32);
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-- Use the simulation interface to set the data we're going to read back
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-- Load up 3 known bytes into the memory
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expected_data := X"AA";
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write_word(rmemory, 0, X"ACABAA");
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-- TB will fault if DUT tries to write to this memory
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set_permissions(rmemory, 0, read_only);
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-- issue spi read command for multiple bytes. No early abort
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for i in 0 to 2 loop
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push_byte(tx_queue, 0); -- push dummy data for the read
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end loop;
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spi_send_stream(net, spi_opcode_read, address, tx_queue, csn);
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-- Read back word rx'd from DUT and check it matches expected.
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-- we're going to have 3 dummy bytes here, skip them, keeping the 4th
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expected_data := X"AA";
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for i in 0 to 4 loop
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pop_stream(net, master_rstream, data);
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-- only check past the dummy data
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if i > 2 then
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check_equal(data, expected_data, "Read data did not match expected, iteration " & to_string(i-2));
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expected_data := expected_data + 1;
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end if;
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end loop;
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elsif run("multi-write") then
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-- set up the "memory to be read with a known value"
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buf := allocate(wmemory, 1 * 64, alignment => 32);
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-- Use the simulation interface to set the data we're expected to write
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set_expected_word(wmemory, 0, X"ACABAA");
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-- issue spi write command
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expected_data := X"AA";
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for i in 0 to 2 loop
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push_byte(tx_queue, to_integer(expected_data)); -- push dummy data for the read
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expected_data := expected_data + 1;
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end loop;
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spi_send_stream(net, spi_opcode_write, address, tx_queue, csn);
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-- no reach into the ram and see what is there now
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wait for 20 ns;
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check_expected_was_written(buf);
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elsif run("ok-after-invalid-opcode") then
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-- set up the "memory to be read with a known value"
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buf := allocate(rmemory, 1 * 64, alignment => 32);
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-- Use the simulation interface to set the data we're going to read back
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expected_data := X"AA";
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write_word(rmemory, 0, expected_data);
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-- TB will fault if DUT tries to write to this memory
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set_permissions(rmemory, 0, read_only);
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-- issue invalid opcode.
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spi_send_byte(net, "1001", address, (others => '0'), csn);
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-- Read back word rx'd from DUT and check it matches expected.
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-- we're going to have 3 dummy bytes here, skip them, keeping the 4th
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for i in 0 to 3 loop
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pop_stream(net, master_rstream, data);
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end loop;
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wait for 20 ns;-- same thing again with a read this time
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-- issue spi read command (data is dummy byte here since this is a)
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spi_send_byte(net, spi_opcode_read, address, (others => '0'), csn);
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-- Read back word rx'd from DUT and check it matches expected.
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-- we're going to have 3 dummy bytes here, skip them, keeping the 4th
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for i in 0 to 3 loop
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pop_stream(net, master_rstream, data);
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end loop;
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check_equal(data, expected_data, "Read data did not match expected");
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end if;
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end loop;
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wait for 2 us;
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test_runner_cleanup(runner);
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wait;
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end process;
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-- Example total test timeout dog
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test_runner_watchdog(runner, 10 ms);
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end tb;

‎hdl/ip/vhd/spi/axi_controller/sims/spi_axi_tb_pkg.vhd

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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
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--
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-- Copyright 2025 Oxide Computer Company
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std_unsigned.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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context vunit_lib.com_context;
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context vunit_lib.vc_context;
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use vunit_lib.spi_pkg.all;
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package spi_axi_tb_pkg is
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constant rd_logger : logger_t := get_logger("axi_rd");
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constant rmemory : memory_t := new_memory;
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constant axi_read_target : axi_slave_t := new_axi_slave(address_fifo_depth => 1,
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memory => rmemory,
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logger => rd_logger);
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constant wr_logger : logger_t := get_logger("axi_wr");
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constant wmemory : memory_t := new_memory;
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constant axi_write_target : axi_slave_t := new_axi_slave(address_fifo_depth => 1,
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memory => wmemory,
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logger => wr_logger);
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constant master_spi : spi_master_t := new_spi_master;
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constant master_wstream : stream_master_t := as_stream(master_spi);
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constant master_rstream : stream_slave_t := as_stream(master_spi);
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procedure spi_send_byte(
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signal net: inout network_t;
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constant opcode: in std_logic_vector(3 downto 0);
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constant addr: in std_logic_vector(15 downto 0);
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constant byte: in std_logic_vector(7 downto 0);
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signal csn : out std_logic
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);
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procedure spi_send_stream(
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signal net: inout network_t;
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constant opcode: in std_logic_vector(3 downto 0);
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constant addr: in std_logic_vector(15 downto 0);
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constant payload_queue: in queue_t;
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signal csn : out std_logic;
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constant cs_abort_after : in natural := 0
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);
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end package;
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package body spi_axi_tb_pkg is
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procedure spi_send_byte(
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signal net: inout network_t;
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constant opcode: in std_logic_vector(3 downto 0);
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constant addr: in std_logic_vector(15 downto 0);
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constant byte: in std_logic_vector(7 downto 0);
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signal csn : out std_logic
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) is
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alias addr_h : std_logic_vector(7 downto 0) is addr(15 downto 8);
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alias addr_l : std_logic_vector(7 downto 0) is addr(7 downto 0);
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begin
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csn <= '0';
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-- read opcode
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push_stream(net, master_wstream, resize(opcode, 8));
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-- addr h
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push_stream(net, master_wstream, addr_h);
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-- addr l
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push_stream(net, master_wstream, addr_l);
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-- data
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push_stream(net, master_wstream, byte);
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wait_until_idle(net, as_sync(master_spi));
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csn <= '1';
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end procedure;
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procedure spi_send_stream(
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signal net: inout network_t;
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constant opcode: in std_logic_vector(3 downto 0);
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constant addr: in std_logic_vector(15 downto 0);
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constant payload_queue: in queue_t;
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signal csn : out std_logic;
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constant cs_abort_after : in natural := 0
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) is
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alias addr_h : std_logic_vector(7 downto 0) is addr(15 downto 8);
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alias addr_l : std_logic_vector(7 downto 0) is addr(7 downto 0);
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variable byte_count : natural := 0;
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begin
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csn <= '0';
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-- read opcode
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push_stream(net, master_wstream, resize(opcode, 8));
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-- addr h
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push_stream(net, master_wstream, addr_h);
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-- addr l
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push_stream(net, master_wstream, addr_l);
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-- data
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while not is_empty(payload_queue) loop
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-- allow for early abort if requested
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if cs_abort_after > 0 and byte_count = cs_abort_after then
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flush(payload_queue);
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csn <= '1';
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exit;
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end if;
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-- otherwise send the next byte and count it
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push_stream(net, master_wstream, to_std_logic_vector(pop_byte(payload_queue), 8));
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byte_count := byte_count + 1;
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end loop;
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wait_until_idle(net, as_sync(master_spi));
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csn <= '1';
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end procedure;
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end package body;

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