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basic-sink: fix message loop exit
1 parent d4c2c02 commit fa7f4cd

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2 files changed

+18
-18
lines changed

2 files changed

+18
-18
lines changed

hdl/ip/vhd/vunit_components/basic_stream/basic_sink.vhd

+1-1
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,9 @@ begin
5656
push_std_ulogic_vector(reply_msg, data);
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reply(net, msg, reply_msg);
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ready <= '0';
59+
exit;
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end if;
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ready <= '0';
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exit;
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end loop;
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else
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unexpected_msg_type(msg_type);

hdl/ip/vhd/vunit_components/basic_stream/sims/th_basic_stream.vhd

+17-17
Original file line numberDiff line numberDiff line change
@@ -31,22 +31,22 @@ begin
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clk <= not clk after 4 ns;
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3333
basic_source_vc : entity work.basic_source
34-
generic map (
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source => source)
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port map (
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clk => clk,
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valid => valid,
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ready => ready,
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data => data
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);
34+
generic map (
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source => source)
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port map (
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clk => clk,
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valid => valid,
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ready => ready,
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data => data
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);
4242

43-
basic_sink_vc : entity work.basic_sink
44-
generic map (
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sink => sink)
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port map (
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clk => clk,
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valid => valid,
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ready => ready,
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data => data
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);
43+
basic_sink_vc : entity work.basic_sink
44+
generic map (
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sink => sink)
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port map (
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clk => clk,
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valid => valid,
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ready => ready,
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data => data
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);
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end architecture;

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