Add a countdown module and make strobe VHDL2008 compliant

hdl/ip/vhd/common/BUCK

@@ -1,34 +1,19 @@
 load("//tools:hdl.bzl", "vhdl_unit")
 
-# Utilities
-
-vhdl_unit(
-    name = "calc_pkg",
-    srcs = ["utils/calc_pkg.vhd",],
-    visibility = ['PUBLIC'],
-)
+# Countdown
 
 vhdl_unit(
-    name = "time_pkg",
-    srcs = ["utils/time_pkg.vhd",],
-    visibility = ['PUBLIC'],
-)
-
-vhdl_unit(
-    name = "transforms_pkg",
-    srcs = ["utils/transforms_pkg.vhd",],
+    name = "countdown",
+    srcs = glob(["countdown/countdown.vhd"]),
+    deps = [],
     visibility = ['PUBLIC'],
 )
 
 vhdl_unit(
-    name = "utilities_tb",
+    name = "countdown_tb",
     is_tb = True,
-    srcs = glob(["utils/sims/*.vhd"]),
-    deps = [
-        ":transforms_pkg", 
-        ":time_pkg", 
-        ":calc_pkg",
-    ],
+    srcs = glob(["countdown/sims/*.vhd"]),
+    deps = [":countdown"],
     visibility = ['PUBLIC'],
 )
 
@@ -48,7 +33,6 @@ vhdl_unit(
     name = "strobe",
     srcs = glob(["strobe/strobe.vhd"]),
     deps = [],
-    standard = "2019",
     visibility = ['PUBLIC'],
 )
 
@@ -57,6 +41,37 @@ vhdl_unit(
     is_tb = True,
     srcs = glob(["strobe/sims/*.vhd"]),
     deps = [":strobe"],
-    standard = "2019",
+    visibility = ['PUBLIC'],
+)
+
+# Utilities
+
+vhdl_unit(
+    name = "calc_pkg",
+    srcs = ["utils/calc_pkg.vhd",],
+    visibility = ['PUBLIC'],
+)
+
+vhdl_unit(
+    name = "time_pkg",
+    srcs = ["utils/time_pkg.vhd",],
+    visibility = ['PUBLIC'],
+)
+
+vhdl_unit(
+    name = "transforms_pkg",
+    srcs = ["utils/transforms_pkg.vhd",],
+    visibility = ['PUBLIC'],
+)
+
+vhdl_unit(
+    name = "utilities_tb",
+    is_tb = True,
+    srcs = glob(["utils/sims/*.vhd"]),
+    deps = [
+        ":transforms_pkg", 
+        ":time_pkg", 
+        ":calc_pkg",
+    ],
     visibility = ['PUBLIC'],
 )

hdl/ip/vhd/common/countdown/countdown.vhd

@@ -0,0 +1,59 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2024 Oxide Computer Company
+
+-- A general purpose counter block which counts down from a supplied `count` to zero. `done is not
+-- registered and will be asserted immediately when the internal count is at zero. Control priority
+-- for the counter is:
+--      1. `clear` will set the counter to zero
+--      2. `load` will set the counter to `count`
+--      3. `decr` will decrement the counter by 1
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+entity countdown is
+    generic (
+        SIZE    : positive
+    );
+    port (
+        clk     : in std_logic;
+        reset   : in std_logic;
+
+        -- target value to count down from
+        count   : in std_logic_vector(SIZE - 1 downto 0);
+        -- loads `count` into internal registers
+        load    : in std_logic;
+        -- decrement internal counter
+        decr    : in std_logic;
+        -- set internal counter to zero
+        clear   : in std_logic;
+
+        -- high if internal counter is equal to zero
+        done    : out std_logic
+    );
+end entity countdown;
+
+architecture rtl of countdown is
+    signal counter  : std_logic_vector(SIZE - 1 downto 0);
+begin
+    counter_gen: process (clk, reset) is
+    begin
+        if reset = '1' then
+            counter <= (others => '0');
+        elsif rising_edge(clk) then
+            if clear then
+                counter <= (others => '0');
+            elsif load then
+                counter <= count;
+            elsif decr then
+                counter <= counter - 1;
+            end if;
+        end if;
+    end process;
+
+    done    <= '1' when counter = 0 else '0';
+end rtl;

hdl/ip/vhd/common/countdown/sims/countdown_tb.gtkw

@@ -0,0 +1,35 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Tue Dec 10 16:14:34 2024
+[*]
+[dumpfile] "/home/aaron/Oxide/git/quartz/vunit_out/test_output/lib.countdown_tb.test_clear_51d615dad8132a3234ef3e09e32429b15166ad96/nvc/countdown_tb.fst"
+[dumpfile_mtime] "Tue Dec 10 16:12:02 2024"
+[dumpfile_size] 682
+[savefile] "/home/aaron/Oxide/git/quartz/hdl/ip/vhd/common/countdown/sims/countdown_tb.gtkw"
+[timestart] 0
+[size] 1296 1283
+[pos] 1215 23
+*-25.634460 208000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] countdown_tb.
+[treeopen] countdown_tb.th.
+[sst_width] 287
+[signals_width] 142
+[sst_expanded] 1
+[sst_vpaned_height] 382
+@28
+countdown_tb.th.clk
+countdown_tb.th.reset
+@200
+-
+-Countdown DUT
+@22
+countdown_tb.th.countdown_inst.count[3:0]
+@28
+countdown_tb.th.countdown_inst.clear
+countdown_tb.th.countdown_inst.load
+countdown_tb.th.countdown_inst.decr
+countdown_tb.th.countdown_inst.done
+@23
+countdown_tb.th.countdown_inst.counter[3:0]
+[pattern_trace] 1
+[pattern_trace] 0

hdl/ip/vhd/common/countdown/sims/countdown_tb.vhd

@@ -0,0 +1,92 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2024 Oxide Computer Company
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.numeric_std_unsigned.all;
+
+library vunit_lib;
+    context vunit_lib.com_context;
+    context vunit_lib.vunit_context;
+    context vunit_lib.vc_context;
+
+entity countdown_tb is
+    generic (
+        runner_cfg : string
+    );
+end entity;
+
+architecture tb of countdown_tb is
+    constant CLK_PER    : time      := 8 ns;
+    constant SIZE       : positive  := 4;
+begin
+
+    th: entity work.countdown_th
+        generic map (
+            CLK_PER => CLK_PER,
+            SIZE    => SIZE
+        );
+
+    bench: process
+        alias reset is << signal th.reset : std_logic >>;
+        alias count is << signal th.dut_count : std_logic_vector >>;
+        alias load is << signal th.dut_load : std_logic >>;
+        alias decr is << signal th.dut_decr : std_logic >>;
+        alias clear is << signal th.dut_clear : std_logic >>;
+        alias done is << signal th.dut_done : std_logic >>;
+    begin
+        -- Always the first thing in the process, set up things for the VUnit test runner
+        test_runner_setup(runner, runner_cfg);
+        -- Reach into the test harness, which generates and de-asserts reset and hold the
+        -- test cases off until we're out of reset. This runs for every test case
+        wait until reset = '0';
+
+        while test_suite loop
+            if run("test_reset") then
+                check_true(done = '1', "should be done as it not been loaded");
+            elsif run("test_clear") then
+                count   <= to_std_logic_vector(3, count'length);
+                load    <= '1';
+                clear   <= '1';
+                wait for CLK_PER;
+                check_true(done = '1', "should be done since clear has priority over load");
+
+                -- load the counter
+                clear   <= '0';
+                wait for CLK_PER;
+                check_true(done = '0', "should not be done after load");
+
+                -- clear the counter
+                clear   <= '1';
+                wait for CLK_PER;
+                check_true(done = '1', "should be done after clear");
+            elsif run("test_countdown") then
+                count   <= to_std_logic_vector(3, count'length);
+                load    <= '1';
+                wait for CLK_PER;
+                check_true(done = '0', "should not be done after load");
+
+                -- count down for a n-1 cycles
+                load    <= '0';
+                decr    <= '1';
+                for i in 0 to 1 loop
+                    wait for CLK_PER;
+                    check_true(done = '0', "should not be done while counting down");
+                end loop;
+
+                -- verify done after the full countdown
+                wait for CLK_PER;
+                check_true(done = '1', "should be done after countdown");
+            end if;
+        end loop;
+
+        wait for 2 us;
+        test_runner_cleanup(runner);
+        wait;
+    end process;
+
+end tb;

hdl/ip/vhd/common/countdown/sims/countdown_th.vhd

@@ -0,0 +1,53 @@
+-- This Source Code Form is subject to the terms of the Mozilla Public
+-- License, v. 2.0. If a copy of the MPL was not distributed with this
+-- file, You can obtain one at https://mozilla.org/MPL/2.0/.
+--
+-- Copyright 2024 Oxide Computer Company
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std_unsigned.all;
+
+library vunit_lib;
+    context vunit_lib.vunit_context;
+    context vunit_lib.com_context;
+    context vunit_lib.vc_context;
+
+entity countdown_th is
+    generic (
+        CLK_PER : time;
+        SIZE    : positive
+    );
+end entity;
+
+architecture th of countdown_th is
+
+    signal clk      : std_logic := '0';
+    signal reset    : std_logic := '1';
+
+    signal dut_count    : std_logic_vector(SIZE - 1 downto 0) := (others => '0');
+    signal dut_load     : std_logic := '0';
+    signal dut_decr     : std_logic := '0';
+    signal dut_clear    : std_logic := '0';
+    signal dut_done     : std_logic := '0';
+
+begin
+
+    clk   <= not clk after CLK_PER / 2;
+    reset <= '0' after 200 ns;
+
+    countdown_inst: entity work.countdown
+     generic map(
+        SIZE => SIZE
+    )
+     port map(
+        clk     => clk,
+        reset   => reset,
+        count   => dut_count,
+        load    => dut_load,
+        decr    => dut_decr,
+        clear   => dut_clear,
+        done    => dut_done
+    );
+
+end th;

hdl/ip/vhd/common/strobe/sims/strobe_tb.vhd

@@ -14,7 +14,6 @@ library vunit_lib;
     context vunit_lib.vunit_context;
     context vunit_lib.vc_context;
 
-
 entity strobe_tb is
     generic (
         runner_cfg : string

hdl/ip/vhd/common/strobe/sims/strobe_th.vhd

@@ -15,7 +15,7 @@ library vunit_lib;
 
 entity strobe_th is
     generic (
-        TICKS : natural
+        TICKS : positive
     );
 end entity;
 

hdl/ip/vhd/common/strobe/strobe.vhd

@@ -18,7 +18,7 @@ entity strobe is
         clk     : in std_logic;
         reset   : in std_logic;
 
-        strobe  : out std_logic;
+        strobe  : out std_logic
     );
 end entity strobe;