RDL naming convention enforcement and updates

hdl/ip/vhd/espi/BUCK

@@ -2,21 +2,21 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
 load("//tools:rdl.bzl", "rdl_file")
 
 rdl_file(
-    name = "espi_spec_regs_pkg",
+    name = "espi_spec_regs_rdl",
     src = "espi_spec_regs.rdl",
     outputs = ["espi_spec_regs_pkg.vhd", "espi_spec_regs.html"],
     visibility = ['PUBLIC']
 )
 
 rdl_file(
-    name = "vwire_regs_pkg",
+    name = "vwire_regs_rdl",
     src = "vwire_channel/vwire_regs.rdl",
     outputs = ["vwire_regs_pkg.vhd", "vwire_regs.html"],
     visibility = ['PUBLIC']
 )
 
 rdl_file(
-    name = "espi_regs_pkg",
+    name = "espi_regs_rdl",
     src = "sys_regs/espi_regs.rdl",
     outputs = ["espi_regs_pkg.vhd", "espi_regs.html"],
     visibility = ['PUBLIC']
@@ -33,9 +33,9 @@ vhdl_unit(
         "vwire_channel/*.vhd",
         "*.vhd"]),
     deps = [
-        ":espi_spec_regs_pkg",
-        ":espi_regs_pkg",
-        ":vwire_regs_pkg",
+        ":espi_spec_regs_rdl",
+        ":espi_regs_rdl",
+        ":vwire_regs_rdl",
         "//hdl/ip/vhd/common:calc_pkg",
         "//hdl/ip/vhd/common:time_pkg",
         "//hdl/ip/vhd/synchronizers:meta_sync",

hdl/ip/vhd/espi/sys_regs/espi_regs.rdl

@@ -2,7 +2,14 @@
 // This is SystemRDL description of the sw-accessible registers in the Gimlet
 // Sequencer FPGA.
 
+property addr_span_bytes {
+    type=number;
+    component=addrmap;
+    default=0x100;
+    };
+
 addrmap espi_regs {
+
     name = "espi system registers";
     desc = "Registers accessible on the Axi bus for debug and testing of the espi target";
 

hdl/ip/vhd/i2c/controller/BUCK

@@ -2,7 +2,7 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
 load("//tools:rdl.bzl", "rdl_file")
 
 rdl_file(
-    name = "i2c_ctrl_regs_pkg",
+    name = "i2c_ctrl_regs_rdl",
     src = "regs/i2c_ctrl_regs.rdl",
     outputs = ["i2c_ctrl_regs_pkg.vhd", "i2c_ctrl_regs.html"],
     visibility = ['PUBLIC']

hdl/ip/vhd/i2c/io_expanders/PCA9506ish/BUCK

@@ -2,9 +2,9 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
 load("//tools:rdl.bzl", "rdl_file")
 
 rdl_file(
-    name = "pca9506_regs_pkg",
+    name = "pca9506_regs_rdl",
     src = "pca9506_regs.rdl",
-    outputs = ["pca9506_regs_pkg.vhd", "pca9506_regs_pkg.html"],
+    outputs = ["pca9506_regs_pkg.vhd", "pca9506_regs.html"],
     visibility = ['PUBLIC']
 )
 
@@ -13,7 +13,7 @@ vhdl_unit(
     srcs = glob(["*.vhd"]),
     deps = [
         "//hdl/ip/vhd/i2c/target:i2c_target_phy",
-        ":pca9506_regs_pkg",
+        ":pca9506_regs_rdl",
     ],
     visibility = ['PUBLIC']
 )

hdl/ip/vhd/i2c/muxes/PCA9545ish/BUCK

@@ -2,9 +2,9 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
 load("//tools:rdl.bzl", "rdl_file")
 
 rdl_file(
-    name = "i2c_mux_regs_pkg",
+    name = "emulated_pca9545_regs_rdl",
     src = "emulated_pca9545_regs.rdl",
-    outputs = ["i2c_mux_regs_pkg.vhd", "i2c_mux_regs.html"],
+    outputs = ["emulated_pca9545_regs_pkg.vhd", "emulated_pca9545_regs.html"],
     visibility = ['PUBLIC']
 )
 
@@ -14,7 +14,7 @@ vhdl_unit(
     srcs = glob(["*.vhd"]),
     deps = [
         "//hdl/ip/vhd/i2c/target:i2c_target_phy",
-        ":i2c_mux_regs_pkg",
+        ":emulated_pca9545_regs_rdl",
     ],
     visibility = ['PUBLIC']
 )

hdl/ip/vhd/i2c/muxes/PCA9545ish/emulated_pca9545_regs.rdl

@@ -1,7 +1,7 @@
 // Copyright 2025 Oxide Computer Company
 // This is SystemRDL description of emulated i2c mux registers
 
-addrmap emulated_pca9545 {
+addrmap emulated_pca9545_regs {
     name = "pca9545 registers";
     desc = "Registers accessible on the i2c bus for controlling the emulated PCA9545 i2c mux";
 

hdl/ip/vhd/i2c/muxes/PCA9545ish/pca9545ish_function.vhd

@@ -16,7 +16,7 @@ use ieee.numeric_std.all;
 use ieee.numeric_std_unsigned.all;
 
 use work.i2c_base_types_pkg.all;
-use work.i2c_mux_regs_pkg.all;
+use work.emulated_pca9545_regs_pkg.all;
 
 
 entity pca9545ish_function is

hdl/ip/vhd/info/BUCK

@@ -2,7 +2,7 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
 load("//tools:rdl.bzl", "rdl_file")
 
 rdl_file(
-    name = "info_regs_pkg",
+    name = "info_regs_rdl",
     src = "info_regs.rdl",
     outputs = ["info_regs_pkg.vhd", "info_regs.html"],
     visibility = ['PUBLIC']
@@ -32,7 +32,7 @@ vhdl_unit(
     srcs = ["info_2k8.vhd"],
     deps = [
         ":git_sha_pkg",
-        ":info_regs_pkg",
+        ":info_regs_rdl",
         ],
     standard = "2008",
     visibility = ['PUBLIC']

hdl/ip/vhd/spi_nor_controller/BUCK

@@ -2,12 +2,12 @@ load("//tools:hdl.bzl", "vhdl_unit", "vunit_sim")
 load("//tools:rdl.bzl", "rdl_file")
 
 rdl_file(
-    name = "spi_nor_rdl",
+    name = "spi_nor_regs_rdl",
     src = "spi_nor_regs.rdl",
     outputs = [
         "spi_nor_regs_pkg.vhd", 
-        "spi_nor_reg_map.html", 
-        "spi_nor_reg_map.json",
+        "spi_nor_regs.html", 
+        "spi_nor_regs.json",
     ],
     visibility = ["PUBLIC"],
 )
@@ -23,7 +23,7 @@ vhdl_unit(
     ]),
     standard = "2019",
     deps = [
-        ":spi_nor_rdl",
+        ":spi_nor_regs_rdl",
         "//hdl/ip/vhd/fifos:dcfifo_xpm",
         "//hdl/ip/vhd/axi_blocks:axilite_if_2k19_pkg",
         ],

hdl/ip/vhd/spi_nor_controller/spi_nor_regs.rdl

@@ -7,7 +7,7 @@
 // This is SystemRDL description of the sw-accesible registers in the
 // grapefruit dev board FPGA.
 
-addrmap nor_flash_regs {
+addrmap spi_nor_regs {
     name = "SPI/QSPI NOR flash controller";
     desc = "";
 

hdl/projects/grapefruit/BUCK

@@ -3,37 +3,37 @@ load("//tools:rdl.bzl", "rdl_file")
 load("//tools:vivado.bzl", "vivado_bitstream")
 
 rdl_file(
-    name = "base_regs_map",
+    name = "gfruit_regs_rdl",
     src = "base_regs/gfruit_regs.rdl",
     outputs = [
-        "grapefruit_regs_pkg.vhd", 
-        "grapefruit_reg_map.html", 
-        "grapefruit_reg_map.json",
+        "gfruit_regs_pkg.vhd", 
+        "gfruit_regs.html", 
+        "gfruit_regs.json",
     ]
 )
 
 rdl_file(
-    name = "gfruit_sgpio_regs",
-    src = "sgpio/gfruit_sgpio.rdl",
+    name = "gfruit_sgpio_regs_rdl",
+    src = "sgpio/gfruit_sgpio_regs.rdl",
     outputs = [
-        "sgpio_regs_pkg.vhd", 
-        "sgpio_reg_map.html", 
-        "sgpio_reg_map.json",
+        "gfruit_sgpio_regs_pkg.vhd", 
+        "gfruit_sgpio_regs.html", 
+        "gfruit_sgpio_regs.json",
     ]
 )
 
 rdl_file(
-    name = "gfruit_top_regs",
+    name = "gfruit_top_rdl",
     src = "gfruit_top.rdl",
     deps = [
-        ":base_regs_map",
-        ":gfruit_sgpio_regs",
-        "//hdl/ip/vhd/spi_nor_controller:spi_nor_rdl",
-        "//hdl/ip/vhd/espi:espi_regs_pkg",
+        ":gfruit_regs_rdl",
+        ":gfruit_sgpio_regs_rdl",
+        "//hdl/ip/vhd/spi_nor_controller:spi_nor_regs_rdl",
+        "//hdl/ip/vhd/espi:espi_regs_rdl",
     ],
     outputs = [
-        "gfruit_top_map.html", 
-        "gfruit_top_map.json"
+        "gfruit_top.html", 
+        "gfruit_top.json"
     ]
 )
 
@@ -46,7 +46,7 @@ vhdl_unit (
     name = "base_regs",
     srcs = glob(["base_regs/*.vhd"]),
     deps = [
-        ":base_regs_map",
+        ":gfruit_regs_rdl",
         "//hdl/ip/vhd/axi_blocks:axilite_if_2k19_pkg",
         ],
     standard = "2019",
@@ -56,7 +56,7 @@ vhdl_unit (
     name = "gfruit_sgpio",
     srcs = glob(["sgpio/*.vhd"]),
     deps = [
-        ":gfruit_sgpio_regs",
+        ":gfruit_sgpio_regs_rdl",
         "//hdl/ip/vhd/axi_blocks:axilite_if_2k19_pkg",
         "//hdl/ip/vhd/sgpio:sgpio_top",
         ],
@@ -69,7 +69,7 @@ vhdl_unit(
     srcs = ["grapefruit_top.vhd"],
     deps = [
         ":base_regs",
-        ":gfruit_top_regs",
+        ":gfruit_top_rdl",
         ":gfruit_sgpio",
         ":gfruit_black_boxes",
         "//hdl/projects/cosmo_seq:reset_sync",

hdl/projects/grapefruit/base_regs/gfruit_regs.rdl

@@ -7,7 +7,7 @@
 // This is SystemRDL description of the sw-accesible registers in the
 // grapefruit dev board FPGA.
 
-addrmap gfruit_base_regs {
+addrmap gfruit_regs {
     name = "Grapefruit FPGA";
     desc = "Register description of the Grapefruit FPGA";
 

hdl/projects/grapefruit/base_regs/registers.vhd

@@ -13,7 +13,7 @@ use ieee.numeric_std_unsigned.all;
 use work.axil_common_pkg.all;
 use work.axil8x32_pkg;
 
-use work.grapefruit_regs_pkg.all;
+use work.gfruit_regs_pkg.all;
 
 entity registers is 
     port (

hdl/projects/grapefruit/gfruit_top.rdl

@@ -1,8 +1,8 @@
 addrmap top_level_map {
     default regwidth = 32;
     // Instantiate 2 to test nesting
-    gfruit_base_regs base @ 0x0;
-    nor_flash_regs spi_nor @ 0x0100;
+    gfruit_regs base @ 0x0;
+    spi_nor_regs spi_nor @ 0x0100;
     espi_regs espi @ 0x0200;
-    gfruit_sgpio sgpio @ 0x0300;
+    gfruit_sgpio_regs sgpio @ 0x0300;
 };

hdl/projects/grapefruit/sgpio/gfruit_sgpio.vhd

@@ -18,7 +18,7 @@ use ieee.numeric_std_unsigned.all;
 
 use work.axil8x32_pkg.all;
 
-use work.sgpio_regs_pkg.all;
+use work.gfruit_sgpio_regs_pkg.all;
 
 entity gfruit_sgpio is
     port (