Make instruction bus delay optional

proteus-core · Dec 19, 2024 · 46534bf · 46534bf
1 parent abb629d
commit 46534bf
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Showing 2 changed files with 19 additions and 7 deletions.
diff --git a/src/main/scala/riscv/Core.scala b/src/main/scala/riscv/Core.scala
@@ -78,12 +78,20 @@ object createStaticPipeline {
 }
 
 object SoC {
-  def static(ramType: RamType, extraDbusReadDelay: Int = 0): SoC = {
-    new SoC(ramType, config => createStaticPipeline()(config), extraDbusReadDelay)
+  def static(
+      ramType: RamType,
+      extraDbusReadDelay: Int = 0,
+      applyDelayToIBus: Boolean = false
+  ): SoC = {
+    new SoC(ramType, config => createStaticPipeline()(config), extraDbusReadDelay, applyDelayToIBus)
   }
 
-  def dynamic(ramType: RamType, extraMemBusDelay: Int = 0): SoC = {
-    new SoC(ramType, config => createDynamicPipeline()(config), extraMemBusDelay)
+  def dynamic(
+      ramType: RamType,
+      extraMemBusDelay: Int = 0,
+      applyDelayToIBus: Boolean = false
+  ): SoC = {
+    new SoC(ramType, config => createDynamicPipeline()(config), extraMemBusDelay, applyDelayToIBus)
   }
 }
 
@@ -168,7 +176,7 @@ object CoreTestSim {
 
 object CoreExtMem {
   def main(args: Array[String]) {
-    SpinalVerilog(SoC.static(RamType.ExternalAxi4(10 MiB), 32))
+    SpinalVerilog(SoC.static(RamType.ExternalAxi4(10 MiB), 32, applyDelayToIBus = false))
   }
 }
 
@@ -313,7 +321,7 @@ object CoreDynamicSim {
 
 object CoreDynamicExtMem {
   def main(args: Array[String]) {
-    SpinalVerilog(SoC.dynamic(RamType.ExternalAxi4(10 MiB), 32))
+    SpinalVerilog(SoC.dynamic(RamType.ExternalAxi4(10 MiB), 32, applyDelayToIBus = false))
   }
 }
 

diff --git a/src/main/scala/riscv/soc/SoC.scala b/src/main/scala/riscv/soc/SoC.scala
@@ -19,7 +19,8 @@ object RamType {
 class SoC(
     ramType: RamType,
     createPipeline: Config => Pipeline,
-    extraMemBusDelay: Int = 0
+    extraMemBusDelay: Int = 0,
+    applyDelayToIBus: Boolean = false
 ) extends Component {
   setDefinitionName("Core")
 
@@ -113,6 +114,9 @@ class SoC(
         dbus.readRsp << crossbar.readRsp.stage(extraMemBusDelay)
         dbus.writeRsp << crossbar.writeRsp
       })
+    }
+
+    if (extraMemBusDelay > 0 && applyDelayToIBus) {
       axiCrossbar.addPipelining(ibusAxi)((ibus, crossbar) => {
         import Utils._