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1 |
| -# TODO |
| 1 | +# SARIS Stencil Kernels |
| 2 | + |
| 3 | +This directory contains the baseline- and SSSR-accelerated Snitch cluster stencil kernels used in the evaluation section of the paper _"SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers"_. In our paper, we describe how indirect stream register architectures such as SSSRs can significantly accelerate stencil codes. |
| 4 | + |
| 5 | +If you use our code or compare against our work, please cite us: |
| 6 | + |
| 7 | +``` |
| 8 | +TODO |
| 9 | +``` |
| 10 | + |
| 11 | +> [!IMPORTANT] |
| 12 | +> - Unlike other software in this repository, compiling this code requires a **custom version of the LLVM 15 toolchain** with some extensions and improvements. The source code for this LLVM fork can be found [here](https://github.com/pulp-platform/llvm-project/tree/15.0.0-saris-0.1.0). |
| 13 | +> - The generated example programs are only intended to be used **in RTL simulation of an SSSR-extended cluster**, using the custom cluster configuration `cfg/sssr.json`. |
| 14 | +
|
| 15 | +## Directory Structure |
| 16 | + |
| 17 | +* `stencils/`: Baseline (`istc.par.hpp`) and SARIS-accelerated (`istc.issr.hpp`) stencil codes. |
| 18 | +* `runtime/`: Additional runtime code and linking configuration needed for compilation. |
| 19 | +* `util/`: Evaluation program generator supporting different grid sizes and kernel calls. |
| 20 | +* `eval.json`: Configuration for test program generator. |
| 21 | + |
| 22 | +## Compile Evaluation Programs |
| 23 | + |
| 24 | +Before you can compile test problems, you need the [SARIS LLVM 15 toolchain](https://github.com/pulp-platform/llvm-project/tree/15.0.0-saris-0.1.0) along with `newlib` and `compiler-rt`. The required build steps are outlined [here](https://github.com/pulp-platform/llvm-toolchain-cd/blob/main/README.md). |
| 25 | + |
| 26 | +Then, you can build the test programs specified in `eval.json` by running: |
| 27 | + |
| 28 | +``` |
| 29 | +make LLVM_BINROOT=<llvm_install_path>/bin all |
| 30 | +``` |
| 31 | + |
| 32 | +By default, `eval.json` specifies RV32G and SSSR-accelerated test programs for all included stencils as specified in our paper. Binaries are generated in `bin/` and disassembled program dumps in `dump/`. |
| 33 | + |
| 34 | + |
| 35 | +## Run Evaluation Programs |
| 36 | + |
| 37 | +Evaluation programs can only be run in RTL simulation of a Snitch cluster using the configuration `cfg/sssr.json`. For example, when building a QuestaSim RTL simulation setup from `target/snitch_cluster`: |
| 38 | + |
| 39 | +``` |
| 40 | +make CFG_OVERRIDE=cfg/sssr.hjson bin/snitch_cluster.vsim |
| 41 | +``` |
| 42 | + |
| 43 | +Then, the built evaluation programs can be run on this simulation setup as usual, for example: |
| 44 | + |
| 45 | +``` |
| 46 | +bin/snitch_cluster.vsim ../../sw/saris/bin/istc.pb_jacobi_2d_ml_issr.elf |
| 47 | +``` |
| 48 | + |
| 49 | +Performance metrics can be analyzed using the annotating Snitch tracer (`make traces`). In the default evaluation programs, the section of interest is section 2. |
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