sw/saris: Switch to, adapt default config, add bib placeholders

Author: paulsc96

README.md

@@ -161,3 +161,21 @@ If you use the Snitch cluster or its extensions in your work, you can cite us:
 ```
 
 </p>
+
+<details>
+<summary><b>SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers</b></summary>
+<p>
+
+```
+@misc{scheffler2024saris,
+      title={SARIS: Accelerating Stencil Computations on Energy-Efficient
+             RISC-V Compute Clusters with Indirect Stream Registers},
+      author={Paul Scheffler and Luca Colagrande and Luca Benini},
+      year={2024},
+      eprint={},
+      archivePrefix={arXiv},
+      primaryClass={cs.MS}
+}
+```
+
+</p>

docs/publications.md

@@ -118,4 +118,22 @@ If you use the Snitch cluster or its extensions in your work, you can cite us:
 
 </p>
 
+<details>
+<summary><b>SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers</b></summary>
+<p>
+
+```
+@misc{scheffler2024saris,
+      title={SARIS: Accelerating Stencil Computations on Energy-Efficient
+             RISC-V Compute Clusters with Indirect Stream Registers},
+      author={Paul Scheffler and Luca Colagrande and Luca Benini},
+      year={2024},
+      eprint={},
+      archivePrefix={arXiv},
+      primaryClass={cs.MS}
+}
+```
+
+</p>
+
 <!--end-publications-->

sw/saris/README.md

@@ -5,12 +5,20 @@ This directory contains the baseline- and SSSR-accelerated Snitch cluster stenci
 If you use our code or compare against our work, please cite us:
 
 ```
-TODO
+@misc{scheffler2024saris,
+      title={SARIS: Accelerating Stencil Computations on Energy-Efficient
+             RISC-V Compute Clusters with Indirect Stream Registers},
+      author={Paul Scheffler and Luca Colagrande and Luca Benini},
+      year={2024},
+      eprint={},
+      archivePrefix={arXiv},
+      primaryClass={cs.MS}
+}
 ```
 
 > [!IMPORTANT]
 > - Unlike other software in this repository, compiling this code requires a **custom version of the LLVM 15 toolchain** with some extensions and improvements. The source code for this LLVM fork can be found [here](https://github.com/pulp-platform/llvm-project/tree/15.0.0-saris-0.1.0).
-> - The generated example programs are only intended to be used **in RTL simulation of an SSSR-extended cluster**, using the custom cluster configuration `cfg/sssr.json`.
+> - The generated example programs are only intended to be used **in RTL simulation of a default, SSSR-extended cluster**, using the cluster configuration `cfg/default.hjson`.
 
 ## Directory Structure
 
@@ -34,10 +42,10 @@ By default, `eval.json` specifies RV32G and SSSR-accelerated test programs for a
 
 ## Run Evaluation Programs
 
-Evaluation programs can only be run in RTL simulation of a Snitch cluster using the configuration `cfg/sssr.json`. For example, when building a QuestaSim RTL simulation setup from `target/snitch_cluster`:
+Evaluation programs can only be run in RTL simulation of a Snitch cluster using the default, SSSR-enhanced configuration `cfg/default.json`. For example, when building a QuestaSim RTL simulation setup from `target/snitch_cluster`:
 
 ```
-make CFG_OVERRIDE=cfg/sssr.hjson bin/snitch_cluster.vsim
+make CFG_OVERRIDE=cfg/default.hjson bin/snitch_cluster.vsim
 ```
 
 Then, the built evaluation programs can be run on this simulation setup as usual, for example:

target/snitch_cluster/cfg/default.hjson

@@ -16,6 +16,7 @@
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
+        user_width: 5, // clog2(total number of clusters)
         tcdm: {
             size: 128,
             banks: 32,
@@ -24,14 +25,28 @@
         zero_mem_size: 64, // kB
         alias_region_enable: true,
         dma_data_width: 512,
-        dma_axi_req_fifo_depth: 3,
-        dma_req_fifo_depth: 3,
+        dma_axi_req_fifo_depth: 24,
+        dma_req_fifo_depth: 8,
+        narrow_trans: 4,
+        wide_trans: 32,
+        dma_user_width: 1,
+        // We don't need Snitch debugging in Occamy
+        enable_debug: false,
+        // We don't need Snitch (core-internal) virtual memory support
+        vm_support: false,
+        // Memory configuration inputs
+        sram_cfg_expose: true,
+        sram_cfg_fields: {
+            ema: 3,
+            emaw: 2,
+            emas: 1
+        },
         // Timing parameters
         timing: {
-            lat_comp_fp32: 3,
+            lat_comp_fp32: 2,
             lat_comp_fp64: 3,
-            lat_comp_fp16: 2,
-            lat_comp_fp16_alt: 2,
+            lat_comp_fp16: 1,
+            lat_comp_fp16_alt: 1,
             lat_comp_fp8: 1,
             lat_comp_fp8_alt: 1,
             lat_noncomp: 1,
@@ -44,7 +59,10 @@
             register_core_req: true,
             register_core_rsp: true,
             register_offload_req: true,
-            register_offload_rsp: true
+            register_offload_rsp: true,
+            register_fpu_req: true,
+            register_ext_narrow: false,
+            register_ext_wide: false
         },
         hives: [
             // Hive 0
@@ -94,15 +112,22 @@
         xf8alt: true,
         xfdotp: true,
         xfvec: true,
+        ssr_nr_credits: 4,
         num_int_outstanding_loads: 1,
         num_int_outstanding_mem: 4,
         num_fp_outstanding_loads: 4,
         num_fp_outstanding_mem: 4,
         num_sequencer_instructions: 16,
         num_dtlb_entries: 1,
         num_itlb_entries: 1,
-        // Enable division/square root unit
-        // Xdiv_sqrt: true,
+        // SSSR configuration below
+        ssr_intersection: true,
+        ssr_intersection_triple: [0, 1, 2],
+        ssrs: [
+            {indirection: true},    // Master 0
+            {indirection: true},    // Master 1
+            {},                     // Slave
+        ],
     },
     dma_core_template: {
         isa: "rv32imafd",