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treewide: Add official riscv-tests ISA tests (#218)
--------- Co-authored-by: Luca Colagrande <luca.colagrande3@gmail.com>
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‎.github/workflows/ci.yml

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@@ -150,6 +150,7 @@ jobs:
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working-directory: target/snitch_cluster
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run: |
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./util/run.py sw/run.yaml --simulator verilator -j
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./util/run.py sw/riscv_tests_isa.yaml --simulator verilator -j
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- name: Annotate traces
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working-directory: target/snitch_cluster
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run: |

‎.gitlab-ci.yml

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@@ -124,6 +124,7 @@ snitch-cluster-vsim:
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- cd target/snitch_cluster
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- make bin/snitch_cluster.vsim
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- ./util/run.py sw/run.yaml --simulator vsim -j --run-dir runs/vsim
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- ./util/run.py sw/riscv_tests_isa.yaml --simulator vsim -j --run-dir runs/vsim
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# Test trace annotation
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- make SIM_DIR=./runs/vsim/simple annotate -j
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# Run additional, more extensive tests

‎.gitmodules

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[submodule "sw/deps/printf"]
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path = sw/deps/printf
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url = https://github.com/mpaland/printf.git
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[submodule "sw/deps/riscv-tests"]
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path = sw/deps/riscv-tests
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url = git@github.com:riscv-software-src/riscv-tests.git

‎sw/deps/riscv-tests

Submodule riscv-tests added at 8d1e1ca

‎target/snitch_cluster/sw.mk

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include sw/toolchain.mk
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include sw/runtime/runtime.mk
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include sw/tests/tests.mk
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include sw/riscv-tests/riscv-tests.mk
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APPS = sw/apps/nop
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APPS += sw/apps/blas/axpy

‎target/snitch_cluster/sw/riscv-tests/riscv-tests.mk

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# Copyright 2025 ETH Zurich and University of Bologna.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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#
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# Pascal Etterli <petterli@student.ethz.ch>
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#
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# This Makefile builds the ISA tests from the RISC-V Test repository.
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# It makes use of the ETHZ LLVM clang infrastructure instead of the provided
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# gcc build setup in the original repository.
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# See also: https://github.com/riscv-software-src/riscv-tests
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##################
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# Test selection #
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##################
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# Sources & destination
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RVT_SCRDIR := $(ROOT)/sw/deps/riscv-tests/isa
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RVT_BUILDDIR := $(ROOT)/target/snitch_cluster/sw/riscv-tests/build/
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# Select the desired test cases
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# We ignore the following tests as we cannot build them with the snitch
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# compiler toolchain.
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# - rv32mi: CSR tcontrol is not recognized
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#
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# We ignore the following test cases as we don't implement the extensions
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# - rv32uc
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# - rv32si
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# - rv32uzfh
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# - rv32uzba
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# - rv32uzbb
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# - rv32uzbc
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# - rv32uzbs
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include $(RVT_SCRDIR)/rv32ui/Makefrag
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# include $(RVT_SCRDIR)/rv32uc/Makefrag
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include $(RVT_SCRDIR)/rv32um/Makefrag
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include $(RVT_SCRDIR)/rv32ua/Makefrag
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include $(RVT_SCRDIR)/rv32uf/Makefrag
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include $(RVT_SCRDIR)/rv32ud/Makefrag
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# include $(RVT_SCRDIR)/rv32uzfh/Makefrag
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# include $(RVT_SCRDIR)/rv32uzba/Makefrag
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# include $(RVT_SCRDIR)/rv32uzbb/Makefrag
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# include $(RVT_SCRDIR)/rv32uzbc/Makefrag
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# include $(RVT_SCRDIR)/rv32uzbs/Makefrag
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# include $(RVT_SCRDIR)/rv32si/Makefrag
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# include $(RVT_SCRDIR)/rv32mi/Makefrag
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###################
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# Build variables #
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###################
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# Provided variables from toolchain.mk
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# - RISCV_CC
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# - RISCV_LD
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# - RISCV_OBJDUMP
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RVT_RISCV_CFLAGS := $(RISCV_CFLAGS) $(RISCV_LDFLAGS)
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RVT_RISCV_CFLAGS += -mno-relax -fvisibility=hidden
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RVT_RISCV_OBJDUMP_FLAGS := $(RISCV_OBJDUMP_FLAGS)
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RVT_RISCV_OBJDUMP_FLAGS += --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
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#########
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# Rules #
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#########
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vpath %.S $(RVT_SCRDIR)
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# Create the objdumps for each compiled program
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%.dump: %
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$(RISCV_OBJDUMP) $(RVT_RISCV_OBJDUMP_FLAGS) $(RVT_BUILDDIR)$<.elf > $(RVT_BUILDDIR)$@
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# Macro to compile each program
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define compile_template
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$$($(1)_p_tests): $(1)-p-%: $(1)/%.S | $(RVT_BUILDDIR)
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$$(RISCV_CC) $$(RVT_RISCV_CFLAGS) -I$(RVT_SCRDIR)/../env/p -I$(RVT_SCRDIR)/macros/scalar -T$(RVT_SCRDIR)/../env/p/link.ld $$< -o $(RVT_BUILDDIR)$$@.elf
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$(1)_tests += $$($(1)_p_tests)
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$$($(1)_v_tests): $(1)-v-%: $(1)/%.S
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$$(RISCV_CC) $$(RVT_RISCV_CFLAGS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(RVT_SCRDIR)/../env/v -I$(RVT_SCRDIR)/macros/scalar -T$(RVT_SCRDIR)/../env/v/link.ld $(RVT_SCRDIR)/../env/v/entry.S $(RVT_SCRDIR)/../env/v/*.c $$< -o $(RVT_BUILDDIR)$$@.elf
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$(1)_tests += $$($(1)_v_tests)
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$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
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$(1): $$($(1)_tests_dump)
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.PHONY: $(1)
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COMPILER_SUPPORTS_$(1) := $$(shell $(RISCV_CC) $(2) -c -x c /dev/null -o /dev/null 2> /dev/null; echo $$$$?)
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ifeq ($$(COMPILER_SUPPORTS_$(1)),0)
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tests += $$($(1)_tests)
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endif
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tests += $$($(1)_tests)
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endef
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# auto generate all test cases. Generates empty ones if Makefrag is not included above
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$(eval $(call compile_template,rv32ui))
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$(eval $(call compile_template,rv32uc))
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$(eval $(call compile_template,rv32um))
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$(eval $(call compile_template,rv32ua))
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$(eval $(call compile_template,rv32uf))
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$(eval $(call compile_template,rv32ud))
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$(eval $(call compile_template,rv32uzfh))
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$(eval $(call compile_template,rv32uzba))
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$(eval $(call compile_template,rv32uzbb))
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$(eval $(call compile_template,rv32uzbc))
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$(eval $(call compile_template,rv32uzbs))
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$(eval $(call compile_template,rv32si))
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$(eval $(call compile_template,rv32mi))
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tests_dump = $(addsuffix .dump, $(tests))
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junk += $(addprefix $(RVT_BUILDDIR),$(addsuffix .elf,$(tests))) $(addprefix $(RVT_BUILDDIR),$(tests_dump))
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$(RVT_BUILDDIR):
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mkdir -p $@
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.PHONY: riscv-tests clean-riscv-tests
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riscv-tests: $(tests_dump) | $(RVT_BUILDDIR)
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clean-riscv-tests:
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rm -rf $(junk)
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# Integrate into main Makefile flow
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sw: riscv-tests
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clean-sw: clean-riscv-tests

‎target/snitch_cluster/sw/riscv_tests_isa.yaml

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# Copyright 2025 ETH Zurich and University of Bologna.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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# Runs riscv-tests ISA test cases for the p environment.
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# Make sure the test cases are compiled in the riscv-tests.mk.
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runs:
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# Base set
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- elf: ./riscv-tests/build/rv32ui-p-simple.elf
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- elf: ./riscv-tests/build/rv32ui-p-sltu.elf
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- elf: ./riscv-tests/build/rv32ui-p-add.elf
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- elf: ./riscv-tests/build/rv32ui-p-addi.elf
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- elf: ./riscv-tests/build/rv32ui-p-xori.elf
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- elf: ./riscv-tests/build/rv32ui-p-and.elf
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- elf: ./riscv-tests/build/rv32ui-p-andi.elf
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- elf: ./riscv-tests/build/rv32ui-p-auipc.elf
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- elf: ./riscv-tests/build/rv32ui-p-beq.elf
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- elf: ./riscv-tests/build/rv32ui-p-bge.elf
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- elf: ./riscv-tests/build/rv32ui-p-bgeu.elf
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- elf: ./riscv-tests/build/rv32ui-p-blt.elf
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- elf: ./riscv-tests/build/rv32ui-p-bltu.elf
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- elf: ./riscv-tests/build/rv32ui-p-bne.elf
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- elf: ./riscv-tests/build/rv32ui-p-sltiu.elf
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- elf: ./riscv-tests/build/rv32ui-p-fence_i.elf
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- elf: ./riscv-tests/build/rv32ui-p-jal.elf
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- elf: ./riscv-tests/build/rv32ui-p-jalr.elf
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- elf: ./riscv-tests/build/rv32ui-p-lb.elf
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- elf: ./riscv-tests/build/rv32ui-p-lbu.elf
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- elf: ./riscv-tests/build/rv32ui-p-lh.elf
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- elf: ./riscv-tests/build/rv32ui-p-lhu.elf
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- elf: ./riscv-tests/build/rv32ui-p-lw.elf
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- elf: ./riscv-tests/build/rv32ui-p-ld_st.elf
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- elf: ./riscv-tests/build/rv32ui-p-lui.elf
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# Exclude the rv32ui-p-ma_data test as it is for user space EEI and assumes that we support
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# unaligned memory access in U mode. Snitch never supports unaligned accesses.
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# - elf: ./riscv-tests/build/rv32ui-p-ma_data.elf
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- elf: ./riscv-tests/build/rv32ui-p-or.elf
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- elf: ./riscv-tests/build/rv32ui-p-ori.elf
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- elf: ./riscv-tests/build/rv32ui-p-sb.elf
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- elf: ./riscv-tests/build/rv32ui-p-sh.elf
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- elf: ./riscv-tests/build/rv32ui-p-sw.elf
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- elf: ./riscv-tests/build/rv32ui-p-st_ld.elf
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- elf: ./riscv-tests/build/rv32ui-p-sll.elf
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- elf: ./riscv-tests/build/rv32ui-p-slli.elf
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- elf: ./riscv-tests/build/rv32ui-p-slt.elf
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- elf: ./riscv-tests/build/rv32ui-p-slti.elf
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- elf: ./riscv-tests/build/rv32ui-p-sra.elf
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- elf: ./riscv-tests/build/rv32ui-p-srai.elf
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- elf: ./riscv-tests/build/rv32ui-p-srl.elf
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- elf: ./riscv-tests/build/rv32ui-p-srli.elf
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- elf: ./riscv-tests/build/rv32ui-p-sub.elf
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- elf: ./riscv-tests/build/rv32ui-p-xor.elf
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# Multiplication
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- elf: ./riscv-tests/build/rv32um-p-div.elf
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- elf: ./riscv-tests/build/rv32um-p-divu.elf
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- elf: ./riscv-tests/build/rv32um-p-mul.elf
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- elf: ./riscv-tests/build/rv32um-p-mulh.elf
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- elf: ./riscv-tests/build/rv32um-p-mulhsu.elf
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- elf: ./riscv-tests/build/rv32um-p-mulhu.elf
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- elf: ./riscv-tests/build/rv32um-p-rem.elf
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- elf: ./riscv-tests/build/rv32um-p-remu.elf
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# Atomics
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- elf: ./riscv-tests/build/rv32ua-p-amomaxu_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-amoor_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-amoand_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-amoadd_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-amomin_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-amomax_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-amoswap_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-amoxor_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-amominu_w.elf
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- elf: ./riscv-tests/build/rv32ua-p-lrsc.elf
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# FLOATING POINT TESTS
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# Some tests could fail because there are additional bits in the fcsr register.
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#
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# The following tests fail because the fcsr read operations are not ordered in regards to the
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# FPU instructions:
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# - elf: ./riscv-tests/build/rv32uf-p-fadd.elf
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# - elf: ./riscv-tests/build/rv32uf-p-fcmp.elf
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# - elf: ./riscv-tests/build/rv32uf-p-fcvt_w.elf
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# - elf: ./riscv-tests/build/rv32uf-p-fmadd.elf
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# - elf: ./riscv-tests/build/rv32uf-p-fmin.elf
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#
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# The fdiv fails because it includes fdiv and fsqrt which both are not supported.
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# - elf: ./riscv-tests/build/rv32uf-p-fdiv.elf
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#
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# The move fails because Snitch has additional custom fcsr CSR bits.
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# - elf: ./riscv-tests/build/rv32uf-p-move.elf
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#
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# The following tests do not check the fcsr value
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- elf: ./riscv-tests/build/rv32uf-p-fclass.elf
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- elf: ./riscv-tests/build/rv32uf-p-fcvt.elf
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- elf: ./riscv-tests/build/rv32uf-p-ldst.elf
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- elf: ./riscv-tests/build/rv32uf-p-recoding.elf
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# DOUBLE TESTS
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# Some tests could fail because there are additional bits in the fcsr register.
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#
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# The following tests fail because the fcsr read operations are not ordered in regards to the
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# FPU instructions:
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# - elf: ./riscv-tests/build/rv32ud-p-fcmp.elf
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# - elf: ./riscv-tests/build/rv32ud-p-fcvt_w.elf
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#
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# The following tests pass only because there are enough integer core instructions between the
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# relevant FPU instruction and its corresponding fcsr read:
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- elf: ./riscv-tests/build/rv32ud-p-fadd.elf
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- elf: ./riscv-tests/build/rv32ud-p-fcvt.elf
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- elf: ./riscv-tests/build/rv32ud-p-fmadd.elf
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- elf: ./riscv-tests/build/rv32ud-p-fmin.elf
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#
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# fdiv tests includes fdiv and fsqrt which both are not supported.
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# - elf: ./riscv-tests/build/rv32ud-p-fdiv.elf
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#
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# The move test is not yet enabled in riscv-tests repo for double. It would probably fail on the
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# additional bits in the fcsr.
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# - elf: no binary yet
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#
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# The following tests do not check the fcsr value
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- elf: ./riscv-tests/build/rv32ud-p-fclass.elf
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- elf: ./riscv-tests/build/rv32ud-p-ldst.elf
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- elf: ./riscv-tests/build/rv32ud-p-recoding.elf

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