@@ -149,37 +149,66 @@ module snitch_cluster_peripheral
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sel_core_events = core_events_i[hart_select];
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sel_dma_events = dma_events_q[hart_select];
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unique case (perf_metrics_q[i])
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- Cycle: perf_cnt_d[i] + = 1 ;
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- TcdmAccessed: perf_cnt_d[i] + = tcdm_events_q.inc_accessed;
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- TcdmCongested: perf_cnt_d[i] + = tcdm_events_q.inc_congested;
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- IssueFpu: perf_cnt_d[i] + = sel_core_events.issue_fpu;
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- IssueFpuSeq: perf_cnt_d[i] + = sel_core_events.issue_fpu_seq;
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- IssueCoreToFpu: perf_cnt_d[i] + = sel_core_events.issue_core_to_fpu;
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- RetiredInstr: perf_cnt_d[i] + = sel_core_events.retired_instr;
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- RetiredLoad: perf_cnt_d[i] + = sel_core_events.retired_load;
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- RetiredI: perf_cnt_d[i] + = sel_core_events.retired_i;
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- RetiredAcc: perf_cnt_d[i] + = sel_core_events.retired_acc;
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- DmaAwStall: perf_cnt_d[i] + = sel_dma_events.aw_stall;
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- DmaArStall: perf_cnt_d[i] + = sel_dma_events.ar_stall;
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- DmaRStall: perf_cnt_d[i] + = sel_dma_events.r_stall;
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- DmaWStall: perf_cnt_d[i] + = sel_dma_events.w_stall;
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- DmaBufWStall: perf_cnt_d[i] + = sel_dma_events.buf_w_stall;
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- DmaBufRStall: perf_cnt_d[i] + = sel_dma_events.buf_r_stall;
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- DmaAwDone: perf_cnt_d[i] + = sel_dma_events.aw_done;
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- DmaAwBw: perf_cnt_d[i] + = ((sel_dma_events.aw_len + 1 ) << (sel_dma_events.aw_size));
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- DmaArDone: perf_cnt_d[i] + = sel_dma_events.ar_done;
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- DmaArBw: perf_cnt_d[i] + = ((sel_dma_events.ar_len + 1 ) << (sel_dma_events.ar_size));
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- DmaRDone: perf_cnt_d[i] + = sel_dma_events.r_done;
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- DmaRBw: perf_cnt_d[i] + = DMADataWidth/ 8 ;
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- DmaWDone: perf_cnt_d[i] + = sel_dma_events.w_done;
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- DmaWBw: perf_cnt_d[i] + = sel_dma_events.num_bytes_written;
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- DmaBDone: perf_cnt_d[i] + = sel_dma_events.b_done;
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- DmaBusy: perf_cnt_d[i] + = sel_dma_events.dma_busy;
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- IcacheMiss: perf_cnt_d[i] + = icache_events_q[hart_select].l0_miss;
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- IcacheHit: perf_cnt_d[i] + = icache_events_q[hart_select].l0_hit;
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- IcachePrefetch: perf_cnt_d[i] + = icache_events_q[hart_select].l0_prefetch;
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- IcacheDoubleHit: perf_cnt_d[i] + = icache_events_q[hart_select].l0_double_hit;
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- IcacheStall: perf_cnt_d[i] + = icache_events_q[hart_select].l0_stall;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__CYCLE: perf_cnt_d[i] + = 1 ;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__TCDM_ACCESSED: perf_cnt_d[i] + =
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+ tcdm_events_q.inc_accessed;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__TCDM_CONGESTED: perf_cnt_d[i] + =
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+ tcdm_events_q.inc_congested;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__ISSUE_FPU: perf_cnt_d[i] + =
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+ sel_core_events.issue_fpu;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__ISSUE_FPU_SEQ: perf_cnt_d[i] + =
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+ sel_core_events.issue_fpu_seq;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__ISSUE_CORE_TO_FPU: perf_cnt_d[i] + =
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+ sel_core_events.issue_core_to_fpu;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__RETIRED_INSTR: perf_cnt_d[i] + =
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+ sel_core_events.retired_instr;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__RETIRED_LOAD: perf_cnt_d[i] + =
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+ sel_core_events.retired_load;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__RETIRED_I: perf_cnt_d[i] + =
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+ sel_core_events.retired_i;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__RETIRED_ACC: perf_cnt_d[i] + =
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+ sel_core_events.retired_acc;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_AW_STALL: perf_cnt_d[i] + =
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+ sel_dma_events.aw_stall;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_AR_STALL: perf_cnt_d[i] + =
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+ sel_dma_events.ar_stall;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_R_STALL: perf_cnt_d[i] + =
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+ sel_dma_events.r_stall;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_W_STALL: perf_cnt_d[i] + =
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+ sel_dma_events.w_stall;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_BUF_W_STALL: perf_cnt_d[i] + =
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+ sel_dma_events.buf_w_stall;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_BUF_R_STALL: perf_cnt_d[i] + =
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+ sel_dma_events.buf_r_stall;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_AW_DONE: perf_cnt_d[i] + =
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+ sel_dma_events.aw_done;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_AW_BW: perf_cnt_d[i] + =
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+ ((sel_dma_events.aw_len + 1 ) << (sel_dma_events.aw_size));
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_AR_DONE: perf_cnt_d[i] + =
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+ sel_dma_events.ar_done;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_AR_BW: perf_cnt_d[i] + =
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+ ((sel_dma_events.ar_len + 1 ) << (sel_dma_events.ar_size));
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_R_DONE: perf_cnt_d[i] + =
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+ sel_dma_events.r_done;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_R_BW: perf_cnt_d[i] + = DMADataWidth/ 8 ;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_W_DONE: perf_cnt_d[i] + =
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+ sel_dma_events.w_done;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_W_BW: perf_cnt_d[i] + =
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+ sel_dma_events.num_bytes_written;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_B_DONE: perf_cnt_d[i] + =
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+ sel_dma_events.b_done;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__DMA_BUSY: perf_cnt_d[i] + =
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+ sel_dma_events.dma_busy;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__ICACHE_MISS: perf_cnt_d[i] + =
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+ icache_events_q[hart_select].l0_miss;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__ICACHE_HIT: perf_cnt_d[i] + =
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+ icache_events_q[hart_select].l0_hit;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__ICACHE_PREFETCH: perf_cnt_d[i] + =
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+ icache_events_q[hart_select].l0_prefetch;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__ICACHE_DOUBLE_HIT: perf_cnt_d[i] + =
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+ icache_events_q[hart_select].l0_double_hit;
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+ snitch_cluster_peripheral_reg__PERF_METRIC__ICACHE_STALL: perf_cnt_d[i] + =
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+ icache_events_q[hart_select].l0_stall;
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default : ;
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endcase
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// Set performance metric.
@@ -213,7 +242,8 @@ module snitch_cluster_peripheral
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if (i < NumPerfMetricRstValues) begin : gen_perf_metrics_rst_value
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`FF (perf_metrics_q[i], perf_metrics_d[i], PerfMetricRstValues[i], clk_i, rst_ni)
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end else begin : gen_perf_metrics_default
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- `FF (perf_metrics_q[i], perf_metrics_d[i], Cycle, clk_i, rst_ni)
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+ `FF (perf_metrics_q[i], perf_metrics_d[i],
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+ snitch_cluster_peripheral_reg__PERF_METRIC__CYCLE, clk_i, rst_ni)
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end
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end
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