test: Remove tb_memory_regbus (#236)

Author: fischeti

Bender.yml

@@ -179,7 +179,6 @@ sources:
   # target/common
   - target: any(simulation, verilator)
     files:
-      - target/common/test/tb_memory_regbus.sv
       - target/common/test/tb_memory_axi.sv
   - target: test
     files:

target/common/test/tb_memory_axi.sv

@@ -28,19 +28,11 @@ module tb_memory_axi #(
   `include "axi/assign.svh"
   `include "axi/typedef.svh"
 
-  `include "register_interface/typedef.svh"
-  `include "register_interface/assign.svh"
-
   `include "common_cells/assertions.svh"
 
   localparam int NumBytes = AxiDataWidth/8;
   localparam int BusAlign = $clog2(NumBytes);
 
-  REG_BUS #(
-    .ADDR_WIDTH ( AxiAddrWidth ),
-    .DATA_WIDTH ( AxiDataWidth )
-  ) regb(clk_i);
-
   AXI_BUS #(
     .AXI_ADDR_WIDTH ( AxiAddrWidth ),
     .AXI_DATA_WIDTH ( AxiDataWidth ),
@@ -88,43 +80,80 @@ module tb_memory_axi #(
     .out (axi_wo_atomics_cut)
   );
 
-  // Convert AXI to a trivial register interface.
-  axi_to_reg_intf #(
-    .ADDR_WIDTH ( AxiAddrWidth ),
-    .DATA_WIDTH ( AxiDataWidth ),
-    .ID_WIDTH   ( AxiIdWidth   ),
-    .USER_WIDTH ( AxiUserWidth ),
-    .DECOUPLE_W ( 1            ),
-    .FULL_BW    ( 1            ),
-    .AXI_MAX_WRITE_TXNS ( 32'd128 ),
-    .AXI_MAX_READ_TXNS  ( 32'd128 )
-  ) i_axi_to_reg (
-    .clk_i,
-    .rst_ni,
-    .testmode_i ( 1'b0 ),
-    .in         ( axi_wo_atomics_cut ),
-    .reg_o      ( regb )
+  logic mem_req;
+  logic mem_gnt;
+  logic [AxiAddrWidth-1:0] mem_addr;
+  logic [AxiDataWidth-1:0] mem_wdata;
+  logic [AxiDataWidth/8-1:0] mem_strb;
+  logic mem_we;
+  logic mem_rvalid;
+  logic [AxiDataWidth-1:0] mem_rdata;
+
+  // Testbench memory is always ready
+  assign mem_gnt = 1'b1;
+  assign mem_rvalid = 1'b1;
+
+  axi_to_mem_intf #(
+    .ADDR_WIDTH    (AxiAddrWidth),
+    .DATA_WIDTH    (AxiDataWidth),
+    .ID_WIDTH      (AxiIdWidth),
+    .USER_WIDTH    (AxiUserWidth),
+    .NUM_BANKS     (1)
+  ) i_axi_to_mem_intf (
+    .clk_i       (clk_i),
+    .rst_ni      (rst_ni),
+    .busy_o      ( ),
+    .slv         (axi_wo_atomics_cut),
+    .mem_req_o   (mem_req),
+    .mem_gnt_i   (mem_gnt),
+    .mem_addr_o  (mem_addr),
+    .mem_wdata_o (mem_wdata),
+    .mem_strb_o  (mem_strb),
+    .mem_atop_o  ( ), // ATOPs are resolved before
+    .mem_we_o    (mem_we),
+    .mem_rvalid_i(mem_req),
+    .mem_rdata_i (mem_rdata)
   );
 
-  `REG_BUS_TYPEDEF_ALL(regbus,
-    logic [AxiAddrWidth-1:0], logic [AxiDataWidth-1:0], logic [NumBytes-1:0])
-
-  regbus_req_t regbus_req;
-  regbus_rsp_t regbus_rsp;
+  import "DPI-C" function void tb_memory_read(
+    input longint addr,
+    input int len,
+    output byte data[]
+  );
+  import "DPI-C" function void tb_memory_write(
+    input longint addr,
+    input int len,
+    input byte data[],
+    input bit strb[]
+  );
 
-  `REG_BUS_ASSIGN_TO_REQ(regbus_req, regb)
-  `REG_BUS_ASSIGN_FROM_RSP(regb, regbus_rsp)
+  // Handle write requests on the mem bus.
+  always_ff @(posedge clk_i) begin
+    if (rst_ni && mem_req) begin
+      automatic byte data[NumBytes];
+      automatic bit  strb[NumBytes];
+      if (mem_we) begin
+        for (int i = 0; i < NumBytes; i++) begin
+          // verilog_lint: waive-start always-ff-non-blocking
+          data[i] = mem_wdata[i*8+:8];
+          strb[i] = mem_strb[i];
+          // verilog_lint: waive-start always-ff-non-blocking
+        end
+        tb_memory_write((mem_addr >> BusAlign) << BusAlign, NumBytes, data, strb);
+      end
+    end
+  end
 
-  tb_memory_regbus #(
-    .AddrWidth (AxiAddrWidth),
-    .DataWidth (AxiDataWidth),
-    .req_t (regbus_req_t),
-    .rsp_t (regbus_rsp_t)
-  ) i_tb_memory_regbus (
-    .clk_i,
-    .rst_ni,
-    .req_i (regbus_req),
-    .rsp_o (regbus_rsp)
-  );
+  // Handle read requests combinatorial on the mem bus.
+  always_comb begin
+    mem_rdata = '0;
+    if (mem_req) begin
+      automatic byte data[NumBytes];
+      tb_memory_read((mem_addr >> BusAlign) << BusAlign, NumBytes, data);
+      for (int i = 0; i < NumBytes; i++) begin
+        mem_rdata[i*8+:8] = data[i];
+      end
+    end
+  end
 
 endmodule