treewide: remove global Python declaration and use venv

Author: Viviane Potocnik

iis-setup.sh

@@ -4,7 +4,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 # Define environment variables
-export PYTHON=/usr/local/anaconda3-2022.05/bin/python3
 export BENDER=bender-0.27.1
 export CC=gcc-9.2.0
 export CXX=g++-9.2.0
@@ -14,7 +13,7 @@ export QUESTA_SEPP=questa-2022.3
 export LLVM_BINROOT=/usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin
 
 # Create Python virtual environment with required packages
-$PYTHON -m venv .venv
+/usr/local/anaconda3-2022.05/bin/python3 -m venv .venv
 source .venv/bin/activate
 # Unpack packages in a local temporary directory which can be safely cleaned
 # after installation. Also protects against "No space left on device" errors

target/common/common.mk

@@ -228,24 +228,24 @@ event-csv: $(EVENT_CSV)
 layout: $(TRACE_CSV) $(TRACE_JSON)
 
 $(LOGS_DIR)/trace_hart_%.txt $(LOGS_DIR)/hart_%_perf.json: $(LOGS_DIR)/trace_hart_%.dasm $(GENTRACE_PY)
-	$(DASM) < $< | $(PYTHON) $(GENTRACE_PY) --permissive -d $(LOGS_DIR)/hart_$*_perf.json > $(LOGS_DIR)/trace_hart_$*.txt
+	$(DASM) < $< | $(GENTRACE_PY) --permissive -d $(LOGS_DIR)/hart_$*_perf.json > $(LOGS_DIR)/trace_hart_$*.txt
 
 # Generate source-code interleaved traces for all harts. Reads the binary from
 # the logs/.rtlbinary file that is written at start of simulation in the vsim script
 BINARY ?= $(shell cat $(SIM_DIR)/.rtlbinary)
 $(LOGS_DIR)/trace_hart_%.s: $(LOGS_DIR)/trace_hart_%.txt ${ANNOTATE_PY}
-	$(PYTHON) ${ANNOTATE_PY} ${ANNOTATE_FLAGS} -o $@ $(BINARY) $<
+	${ANNOTATE_PY} ${ANNOTATE_FLAGS} -o $@ $(BINARY) $<
 $(LOGS_DIR)/trace_hart_%.diff: $(LOGS_DIR)/trace_hart_%.txt ${ANNOTATE_PY}
-	$(PYTHON) ${ANNOTATE_PY} ${ANNOTATE_FLAGS} -o $@ $(BINARY) $< -d
+	${ANNOTATE_PY} ${ANNOTATE_FLAGS} -o $@ $(BINARY) $< -d
 
 $(PERF_CSV): $(PERF_TRACES) $(PERF_CSV_PY)
-	$(PYTHON) $(PERF_CSV_PY) -o $@ -i $(PERF_TRACES)
+	$(PERF_CSV_PY) -o $@ -i $(PERF_TRACES)
 
 $(EVENT_CSV): $(PERF_TRACES) $(PERF_CSV_PY)
-	$(PYTHON) $(PERF_CSV_PY) -o $@ -i $(PERF_TRACES) --filter tstart tend
+	$(PERF_CSV_PY) -o $@ -i $(PERF_TRACES) --filter tstart tend
 
 $(TRACE_CSV): $(EVENT_CSV) $(LAYOUT_FILE) $(LAYOUT_EVENTS_PY)
-	$(PYTHON) $(LAYOUT_EVENTS_PY) $(LAYOUT_EVENTS_FLAGS) $(EVENT_CSV) $(LAYOUT_FILE) -o $@
+	$(LAYOUT_EVENTS_PY) $(LAYOUT_EVENTS_FLAGS) $(EVENT_CSV) $(LAYOUT_FILE) -o $@
 
 $(TRACE_JSON): $(TRACE_CSV) $(EVENTVIS_PY)
-	$(PYTHON) $(EVENTVIS_PY) -o $@ $(TRACE_CSV)
+	$(EVENTVIS_PY) -o $@ $(TRACE_CSV)

target/snitch_cluster/sw/apps/blas/gemm/test/test.sh

@@ -13,5 +13,5 @@ TEST_LIST=$(pwd)/run.yaml
 CFG_FILES=$(pwd)/cfg/"*"
 CMD="$ROOT/sw/blas/gemm/scripts/verify.py \${sim_bin} \${elf} --dump-results"
 
-$PYTHON $BUILD_PY sw/apps/blas/gemm --cfg $CFG_FILES --testlist $TEST_LIST --testlist-cmd "$CMD"
-$PYTHON $RUN_PY $TEST_LIST --simulator vsim -j
+$BUILD_PY sw/apps/blas/gemm --cfg $CFG_FILES --testlist $TEST_LIST --testlist-cmd "$CMD"
+$RUN_PY $TEST_LIST --simulator vsim -j

target/snitch_cluster/sw/apps/dnn/flashattention_2/test/test.sh

@@ -12,5 +12,5 @@ TEST_LIST=$(pwd)/run.yaml
 CFG_FILES=$(pwd)/cfg/"*"
 CMD="$ROOT/sw/dnn/flashattention_2/scripts/verify.py \${sim_bin} \${elf} --dump-results"
 
-$PYTHON $BUILD_PY sw/apps/dnn/flashattention_2 --cfg $CFG_FILES --testlist $TEST_LIST --testlist-cmd "$CMD"
-$PYTHON $RUN_PY $TEST_LIST --simulator vsim -j
+$BUILD_PY sw/apps/dnn/flashattention_2 --cfg $CFG_FILES --testlist $TEST_LIST --testlist-cmd "$CMD"
+$RUN_PY $TEST_LIST --simulator vsim -j

target/snitch_cluster/sw/apps/dnn/transpose/test/test.sh

@@ -12,5 +12,5 @@ TEST_LIST=$(pwd)/run.yaml
 CFG_FILES=$(pwd)/cfg/"*"
 CMD="$ROOT/sw/dnn/transpose/scripts/verify.py \${sim_bin} \${elf} --dump-results"
 
-$PYTHON $BUILD_PY sw/apps/dnn/transpose --cfg $CFG_FILES --testlist $TEST_LIST --testlist-cmd "$CMD"
-$PYTHON $RUN_PY $TEST_LIST --simulator vsim -j
+$BUILD_PY sw/apps/dnn/transpose --cfg $CFG_FILES --testlist $TEST_LIST --testlist-cmd "$CMD"
+$RUN_PY $TEST_LIST --simulator vsim -j