tests: Added support for gvsoc

Author: Germain Haugou

target/common/common.mk

@@ -50,6 +50,8 @@ SED_SRCS  := sed -e ${MATCH_END} -e ${MATCH_BGN} -e ${MATCH_DEF}
 
 COMMON_BENDER_FLAGS += -t rtl
 
+GVSOC_BUILDDIR ?= work-gvsoc
+
 VSIM_BENDER   += $(COMMON_BENDER_FLAGS) -t test -t simulation -t vsim
 VSIM_SOURCES   = $(shell ${BENDER} script flist-plus ${VSIM_BENDER} | ${SED_SRCS})
 VSIM_BUILDDIR ?= work-vsim

target/common/gvsoc.mk

@@ -0,0 +1,21 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+$(BIN_DIR)/$(TARGET).gvsoc:
+	@echo "#!/bin/bash" > $@
+	@echo 'binary=$$(realpath $$1)' >> $@
+	@echo 'echo $$binary > .rtlbinary' >> $@
+	@echo 'path="$$(dirname "$$(dirname "$$(readlink -f "$${BASH_SOURCE[0]}")")")"' >> $@
+	@echo 'if [ -z "$$GVSOC_TARGET" ]; then' >> $@
+	@echo '    GVSOC_TARGET=snitch' >> $@
+	@echo 'fi' >> $@
+	@echo 'gvsoc --target=$${GVSOC_TARGET} --binary $$binary \
+	   --control-script=$${path}/../../util/sim/gvsoc_control.py $$2 run' >> $@
+	@chmod +x $@
+
+.PHONY: clean-gvsoc
+clean-gvsoc:
+	rm -rf $(BIN_DIR)/$(TARGET).gvsoc $(GVSOC_BUILDDIR)
+
+clean: clean-gvsoc

target/snitch_cluster/Makefile

@@ -215,6 +215,12 @@ $(BIN_DIR)/$(TARGET).vcs: ${VCS_SOURCES} ${TB_SRCS} $(TB_CC_SOURCES) $(RTL_CC_SO
 		-assert disable_cover -override_timescale=1ns/1ps -full64 tb_bin $(TB_CC_SOURCES) $(RTL_CC_SOURCES) \
 		-CFLAGS "$(TB_CC_FLAGS)" -LDFLAGS "-L${FESVR}/lib" -lfesvr
 
+#########
+# GVSOC #
+#########
+
+include $(ROOT)/target/common/gvsoc.mk
+
 ########
 # Util #
 ########

target/snitch_cluster/sw/run.yaml

@@ -6,60 +6,66 @@ runs:
   - elf: tests/build/alias.elf
     simulators: [vsim, vcs, verilator] # banshee does not model alias regions
   - elf: tests/build/atomics.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x4
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x4
   - elf: tests/build/barrier.elf
   - elf: tests/build/data_mover.elf
+    simulators: [vsim, vcs, verilator, banshee]
   - elf: tests/build/dma_empty_transfer.elf
   - elf: tests/build/dma_simple.elf
   - elf: tests/build/event_unit.elf
+    simulators: [vsim, vcs, verilator, banshee]
   - elf: tests/build/fence_i.elf
   - elf: tests/build/fp8_comparison_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with segfault
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with segfault
   - elf: tests/build/fp8_comparison_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with segfault
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with segfault
   - elf: tests/build/fp8_computation_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with JIT issue
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with JIT issue
   - elf: tests/build/fp8_computation_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x6
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x6
   - elf: tests/build/fp8alt_comparison_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with segfault
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with segfault
   - elf: tests/build/fp8alt_comparison_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x10
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x10
   - elf: tests/build/fp8alt_computation_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with JIT issue
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with JIT issue
   - elf: tests/build/fp8alt_computation_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x12
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x12
   - elf: tests/build/fp16_comparison_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x10
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x10
   - elf: tests/build/fp16_comparison_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x10
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x10
   - elf: tests/build/fp16_computation_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with JIT issue
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with JIT issue
   - elf: tests/build/fp16_computation_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x6
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x6
   - elf: tests/build/fp16alt_comparison_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x10
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x10
   - elf: tests/build/fp16alt_comparison_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x10
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x10
   - elf: tests/build/fp16alt_computation_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with JIT issue
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with JIT issue
   - elf: tests/build/fp16alt_computation_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x16
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x16
   - elf: tests/build/fp32_comparison_scalar.elf
   - elf: tests/build/fp32_comparison_vector.elf
   - elf: tests/build/fp32_computation_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x2
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x2
   - elf: tests/build/fp32_computation_vector.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with exit code 0x2
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with exit code 0x2
   - elf: tests/build/fp32_conversions_scalar.elf
-    simulators: [vsim, vcs, verilator] # banshee fails with illegal instruction
+    simulators: [vsim, vcs, verilator, gvsoc] # banshee fails with illegal instruction
   # - elf: tests/build/fp64_conversions_scalar.elf
   #   simulators: [vsim, vcs, verilator]
   - elf: tests/build/interrupt_local.elf
+    simulators: [vsim, vcs, verilator, banshee]
   - elf: tests/build/multi_cluster.elf
   - elf: tests/build/openmp_parallel.elf
+    simulators: [vsim, vcs, verilator, banshee]
   - elf: tests/build/openmp_for_static_schedule.elf
+    simulators: [vsim, vcs, verilator, banshee]
   - elf: tests/build/openmp_double_buffering.elf
+    simulators: [vsim, vcs, verilator, banshee]
   - elf: tests/build/perf_cnt.elf
     simulators: [vsim, vcs, verilator] # banshee does not have HW performance counters
   - elf: tests/build/printf_simple.elf
@@ -72,6 +78,7 @@ runs:
   - elf: tests/build/non_null_exitcode.elf
     retcode: 56
   - elf: tests/build/caq.elf
+    simulators: [vsim, vcs, verilator, banshee] # GVSOC does not model caq
   - elf: tests/build/caq_frep.elf
     simulators: [vsim, vcs, verilator] # banshee does not model FREP timing
   - elf: apps/blas/axpy/build/axpy.elf
@@ -93,11 +100,13 @@ runs:
   - elf: apps/dnn/fused_concat_linear/build/fused_concat_linear.elf
     cmd: [../../../sw/dnn/fused_concat_linear/scripts/verify.py, "${sim_bin}", "${elf}"]
   - elf: apps/dnn/transpose/build/transpose.elf
+    simulators: [vsim, vcs, verilator, banshee]
     cmd: [../../../sw/dnn/transpose/scripts/verify.py, "${sim_bin}", "${elf}"]
   - elf: apps/montecarlo/pi_estimation/build/pi_estimation.elf
   - elf: apps/atax/build/atax.elf
     cmd: [../../../sw/apps/atax/scripts/verify.py, "${sim_bin}", "${elf}"]
   - elf: apps/covariance/build/covariance.elf
+    simulators: [vsim, vcs, verilator, banshee]
     cmd: [../../../sw/apps/covariance/scripts/verify.py, "${sim_bin}", "${elf}"]
   - elf: apps/doitgen/build/doitgen.elf
     cmd: [../../../sw/apps/doitgen/scripts/verify.py, "${sim_bin}", "${elf}"]

target/snitch_cluster/util/run.py

@@ -15,15 +15,16 @@
 
 sys.path.append(str(Path(__file__).parent / '../../../util/sim'))
 import sim_utils  # noqa: E402
-from Simulator import QuestaSimulator, VCSSimulator, VerilatorSimulator, \
+from Simulator import QuestaSimulator, VCSSimulator, VerilatorSimulator, GvsocSimulator, \
                       BansheeSimulator  # noqa: E402
 
 
 SIMULATORS = {
     'vsim': QuestaSimulator(Path(__file__).parent.resolve() / '../bin/snitch_cluster.vsim'),
     'vcs': VCSSimulator(Path(__file__).parent.resolve() / '../bin/snitch_cluster.vcs'),
     'verilator': VerilatorSimulator(Path(__file__).parent.resolve() / '../bin/snitch_cluster.vlt'),
-    'banshee': BansheeSimulator(Path(__file__).parent.resolve() / '../src/banshee.yaml')
+    'banshee': BansheeSimulator(Path(__file__).parent.resolve() / '../src/banshee.yaml'),
+    'gvsoc': GvsocSimulator(Path(__file__).parent.resolve() / '../bin/snitch_cluster.gvsoc')
 }
 
 

util/sim/Simulation.py

@@ -267,6 +267,37 @@ def get_cpu_time(self):
                         return hours*3600 + minutes*60 + seconds
 
 
+class GvsocSimulation(Simulation):
+    """A functional simulation running on GVSOC."""
+
+    def __init__(self, sim_bin=None, cmd=None, **kwargs):
+        super().__init__(**kwargs)
+
+        if cmd is None:
+            self.cmd = ['gvsoc', '--target', os.environ.get('GVSOC_TARGET'), '--binary',
+                        str(self.elf), 'run']
+        else:
+            self.dynamic_args = {
+                'sim_bin': str(sim_bin),
+                'elf': str(self.elf),
+                'run_dir': str(self.run_dir)
+            }
+            self.cmd = [Template(arg).render(**self.dynamic_args) for arg in cmd]
+            self.cmd.append('--simulator=gvsoc')
+
+    def successful(self):
+        """Return whether the simulation was successful."""
+        # On GVSOC, OpenOCD semi-hosting is used which can just report 0 or 1
+        actual_retcode = self.get_retcode()
+        if actual_retcode is not None:
+            if self.expected_retcode != 0:
+                return int(actual_retcode) != 0
+            else:
+                return int(actual_retcode) == 0
+        else:
+            return False
+
+
 class VCSSimulation(QuestaVCSSimulation):
     """An RTL simulation running on VCS."""
 

util/sim/Simulator.py

@@ -4,7 +4,8 @@
 #
 # Luca Colagrande <colluca@iis.ee.ethz.ch>
 
-from Simulation import QuestaSimulation, VCSSimulation, VerilatorSimulation, BansheeSimulation
+from Simulation import QuestaSimulation, VCSSimulation, VerilatorSimulation, BansheeSimulation, \
+    GvsocSimulation
 
 
 class Simulator(object):
@@ -97,6 +98,36 @@ def get_simulation(self, test):
         )
 
 
+class GvsocSimulator(Simulator):
+    """Gvsoc simulator
+
+    A simulator, identified by the name
+    `gvsoc`, tailored to the creation of
+    [Gvsoc simulations][Simulation.GvsocSimulation].
+    """
+
+    def __init__(self, binary):
+        """Constructor for the GvsocSimulator class.
+
+        Arguments:
+            binary: The Gvsoc simulation binary.
+            kwargs: Arguments passed to the base class constructor.
+        """
+        super().__init__(name='gvsoc', simulation_cls=GvsocSimulation)
+        self.binary = binary
+
+    def get_simulation(self, test):
+        if 'cmd' in test:
+            cmd = test['cmd']
+        else:
+            cmd = None
+        return super().get_simulation(
+            test,
+            sim_bin=self.binary,
+            cmd=cmd
+        )
+
+
 class VCSSimulator(RTLSimulator):
     """VCS simulator
 

util/sim/SnitchSim.py

@@ -25,11 +25,12 @@
 
 class SnitchSim:
 
-    def __init__(self, sim_bin: str, snitch_bin: str, log: str = None):
+    def __init__(self, sim_bin: str, snitch_bin: str, simulator: str = None, log: str = None):
         self.sim_bin = sim_bin
         self.snitch_bin = snitch_bin
         self.sim = None
         self.tmpdir = None
+        self.simulator = simulator
         self.log = open(log, 'w+') if log else log
 
     def start(self):
@@ -40,7 +41,11 @@ def start(self):
         rx_fd = os.path.join(self.tmpdir.name, 'rx')
         os.mkfifo(rx_fd)
         # Start simulator process
-        ipc_arg = f'--ipc,{tx_fd},{rx_fd}'
+        if self.simulator == 'gvsoc':
+            ipc_arg = f'--ipc {tx_fd},{rx_fd}'
+        else:
+            ipc_arg = f'--ipc,{tx_fd},{rx_fd}'
+
         self.sim = subprocess.Popen([self.sim_bin, self.snitch_bin, ipc_arg], stdout=self.log)
         # Open FIFOs
         self.tx = open(tx_fd, 'wb', buffering=0)  # Unbuffered

util/sim/gvsoc_control.py

@@ -0,0 +1,61 @@
+#!/usr/bin/env python3
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Author: Germain Haugou <haugoug@iis.ee.ethz.ch>
+
+import gvsoc.gvsoc_control
+import struct
+
+
+def parse_args(parser, args):
+    parser.add_argument('--ipc', type=str, help="IPC socket files")
+
+
+def handle_commands(gv, tx_fd, rx_fd):
+
+    axi = gvsoc.gvsoc_control.Router(gv, path='**/chip/soc/narrow_axi')
+
+    gv.run()
+
+    while True:
+        data = rx_fd.read(8)
+        if not data:
+            return
+
+        command = struct.unpack('=Q', data)[0]
+
+        if command == 2:
+            data = rx_fd.read(16)
+            addr, mask32, exp32 = struct.unpack('=QLL', data)
+
+            retval = gv.join()
+            data = struct.pack('=L', retval)
+            tx_fd.write(data)
+
+        elif command == 0:
+            data = rx_fd.read(16)
+            addr, length = struct.unpack('=QQ', data)
+            data = axi.mem_read(addr, length)
+            tx_fd.write(data)
+
+        elif command == 1:
+            data = rx_fd.read(16)
+            addr, length = struct.unpack('=QQ', data)
+            data = rx_fd.read(length)
+            axi.mem_write(addr, data)
+            data = struct.pack('=L', 0)
+            tx_fd.write(data)
+            pass
+
+
+def target_control(args, gv=None):
+    rx, tx = args.ipc.split(',')
+
+    rx_fd = open(rx, 'rb', buffering=0)
+    tx_fd = open(tx, 'wb', buffering=0)
+
+    handle_commands(gv, tx_fd, rx_fd)
+
+    return 0

util/sim/verif_utils.py

@@ -97,6 +97,9 @@ def parser(self):
         parser.add_argument(
             '--log',
             help='Redirect simulation output to this log file')
+        parser.add_argument(
+            '--simulator',
+            help='Specifies simulator')
         parser.add_argument(
             '--dump-results',
             action='store_true',
@@ -144,7 +147,8 @@ def simulate(self):
         elf = Elf(self.args.snitch_bin)
 
         # Start simulation
-        sim = SnitchSim(self.args.sim_bin, self.args.snitch_bin, log=self.args.log)
+        sim = SnitchSim(self.args.sim_bin, self.args.snitch_bin, simulator=self.args.simulator,
+            log=self.args.log)
         sim.start()
 
         # Wait for kernel execution to be over