treewide: Add multicast support (#234)

* treewide: Add wide multicast support

* treewide: Add narrow multicast support

* sw: Fix runtime to support multi cluster systems

* ci: Sanitize repo name for Docker tag name

---------

Co-authored-by: Luca Colagrande <luca.colagrande3@gmail.com>

Author: Lore0599

.github/workflows/ci.yml

@@ -27,11 +27,13 @@ jobs:
       - name: Define Docker image name
         id: image_name
         # To satisfy Docker tag naming requirements, we replace all slashes
-        # in the ref name with dashes.
+        # in the ref name with hyphens and convert the repository name to lowercase.
         run: |
           SANITIZED_REF_NAME="${GITHUB_REF_NAME//\//-}"
           echo "Sanitized GITHUB_REF_NAME: $SANITIZED_REF_NAME"
-          IMAGE_NAME="ghcr.io/${GITHUB_REPOSITORY}:${SANITIZED_REF_NAME}"
+          SANITIZED_REPO_NAME="$(echo "${GITHUB_REPOSITORY}" | tr '[:upper:]' '[:lower:]')"
+          echo "Sanitized GITHUB_REPOSITORY: $SANITIZED_REPO_NAME"
+          IMAGE_NAME="ghcr.io/${SANITIZED_REPO_NAME}:${SANITIZED_REF_NAME}"
           echo "Image name: $IMAGE_NAME"
           echo "image_name=$IMAGE_NAME" >> $GITHUB_OUTPUT
       - name: Free Disk Space (Ubuntu)

Bender.lock

@@ -7,10 +7,10 @@ packages:
     dependencies:
     - common_cells
   axi:
-    revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7
-    version: 0.39.6
+    revision: bec548fa2a9b18cbd7531105bb1fdf481ea8ad49
+    version: null
     source:
-      Git: https://github.com/pulp-platform/axi
+      Git: https://github.com/colluca/axi.git
     dependencies:
     - common_cells
     - common_verification
@@ -42,8 +42,8 @@ packages:
     - scm
     - tech_cells_generic
   common_cells:
-    revision: 9afda9abb565971649c2aa0985639c096f351171
-    version: 1.38.0
+    revision: 265b4cf5fe561cb837899c580f392ea93bf7e147
+    version: null
     source:
       Git: https://github.com/pulp-platform/common_cells
     dependencies:
@@ -71,10 +71,10 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: ff5d56fffb3767814db88d6bf8f381974ea33aa5
-    version: 0.6.4
+    revision: c396bbf477457b184a74b7f2386302f5895bb522
+    version: null
     source:
-      Git: https://github.com/pulp-platform/iDMA
+      Git: https://github.com/pulp-platform/iDMA.git
     dependencies:
     - axi
     - axi_stream

Bender.yml

@@ -19,15 +19,15 @@ package:
     - Matheus Cavalcante <matheusd@iis.ee.ethz.ch>
 
 dependencies:
-  axi:                { git: https://github.com/pulp-platform/axi,                version:  0.39.6      }
+  axi:                { git: https://github.com/colluca/axi,                      rev:  multicast       }
   axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version:  0.6.0       }
-  common_cells:       { git: https://github.com/pulp-platform/common_cells,       version:  1.35.0      }
+  common_cells:       { git: https://github.com/pulp-platform/common_cells,       rev:  multicast-xbar  }
   FPnew:              { git: https://github.com/pulp-platform/cvfpu.git,          rev:      pulp-v0.1.3 }
   register_interface: { git: https://github.com/pulp-platform/register_interface, version:  0.4.2       }
   tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.13      }
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0       }
   cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, rev: 64e21ae455bbdde850c4df13bef86ea55ac42537 }
-  idma:               { git: https://github.com/pulp-platform/iDMA,               version:  0.6.4       }
+  idma:               { git: https://github.com/pulp-platform/iDMA.git,           rev: __deploy__3c6bbb7__multicast-integration }
 
 export_include_dirs:
   - hw/reqrsp_interface/include

hw/reqrsp_interface/include/reqrsp_interface/typedef.svh

@@ -11,6 +11,7 @@
 `define REQRSP_TYPEDEF_REQ_CHAN_T(__req_chan_t, __addr_t, __data_t, __strb_t) \
   typedef struct packed { \
     __addr_t             addr;  \
+    __addr_t             mask;  \
     logic                write; \
     reqrsp_pkg::amo_op_e amo;   \
     __data_t             data;  \

hw/reqrsp_interface/src/axi_to_reqrsp.sv

@@ -303,7 +303,8 @@ module axi_to_reqrsp #(
     // Silence those channels in case of a read.
     data: data & {DataWidth{meta.write}},
     strb: axi_req_i.w.strb & {StrbWidth{meta.write}},
-    size: meta.size
+    size: meta.size,
+    default: '0
   };
 
   always_comb begin

hw/snitch/src/riscv_instr.sv

@@ -327,6 +327,7 @@ package riscv_instr;
   localparam logic [31:0] DMSTAT             = 32'b0000101?????00000000?????0101011;
   localparam logic [31:0] DMSTR              = 32'b0000110??????????000000000101011;
   localparam logic [31:0] DMREP              = 32'b000011100000?????000000000101011;
+  localparam logic [31:0] DMMCAST            = 32'b000100000000?????000000000101011;
   localparam logic [31:0] FREP_O             = 32'b????????????????????????10001011;
   localparam logic [31:0] FREP_I             = 32'b????????????????????????00001011;
   localparam logic [31:0] IREP               = 32'b?????????????????????????0111111;
@@ -1140,6 +1141,7 @@ package riscv_instr;
   localparam logic [11:0] CSR_FPMODE = 12'h7c1;
   localparam logic [11:0] CSR_BARRIER = 12'h7c2;
   localparam logic [11:0] CSR_SC = 12'h7c3;
+  localparam logic [11:0] CSR_MCAST = 12'h7c4;
   localparam logic [11:0] CSR_HTIMEDELTAH = 12'h615;
   localparam logic [11:0] CSR_CYCLEH = 12'hc80;
   localparam logic [11:0] CSR_TIMEH = 12'hc81;

hw/snitch/src/snitch.sv

@@ -248,6 +248,8 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   logic csr_en;
   logic csr_dump;
   logic csr_stall_d, csr_stall_q;
+  // Multicast mask
+  logic [31:0] csr_mcast_d, csr_mcast_q;
 
   localparam logic M = 0;
   localparam logic S = 1;
@@ -317,6 +319,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
   end
 
   `FFAR(csr_stall_q, csr_stall_d, '0, clk_i, rst_i)
+  `FFAR(csr_mcast_q, csr_mcast_d, '0, clk_i, rst_i)
 
   typedef struct packed {
     fpnew_pkg::fmt_mode_t  fmode;
@@ -2220,6 +2223,16 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
           illegal_inst = 1'b1;
         end
       end
+      DMMCAST: begin
+        if (Xdma) begin
+          acc_qreq_o.addr = DMA_SS;
+          opa_select      = Reg;
+          acc_qvalid_o    = valid_instr;
+          write_rd        = 1'b0;
+        end else begin
+          illegal_inst = 1'b1;
+        end
+      end
       SCFGRI: begin
         if (Xssr) begin
           write_rd = 1'b0;
@@ -2345,6 +2358,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
     dscratch_d = dscratch_q;
 
     csr_stall_d = csr_stall_q;
+    csr_mcast_d = csr_mcast_q;
 
     if (barrier_i) csr_stall_d = 1'b0;
     barrier_o = 1'b0;
@@ -2568,6 +2582,11 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
             barrier_o = 1'b1;
             csr_stall_d = 1'b1;
           end
+          // Multicast mask
+          CSR_MCAST: begin
+            csr_rvalue = csr_mcast_q;
+            csr_mcast_d = alu_result[31:0];
+          end
           default: begin
             csr_rvalue = '0;
             csr_dump = 1'b1;
@@ -2888,6 +2907,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #(
     .lsu_qsize_i (ls_size),
     .lsu_qamo_i (ls_amo),
     .lsu_qrepd_i (1'b0),
+    .lsu_qmcast_i (addr_t'(csr_mcast_q)),
     .lsu_qvalid_i (lsu_qvalid),
     .lsu_qready_o (lsu_qready),
     .lsu_pdata_o (ld_result),

hw/snitch/src/snitch_lsu.sv

@@ -52,6 +52,7 @@ module snitch_lsu #(
   input  logic [1:0]           lsu_qsize_i,
   input  reqrsp_pkg::amo_op_e  lsu_qamo_i,
   input  logic                 lsu_qrepd_i,  // Whether this is a sequencer repetition
+  input  addr_t                lsu_qmcast_i,  // Multicast mask
   input  logic                 lsu_qvalid_i,
   output logic                 lsu_qready_o,
   // response channel
@@ -250,6 +251,7 @@ module snitch_lsu #(
   assign data_req_o.q_valid = lsu_postcaq_qvalid & (lsu_qwrite_i | ~laq_full) & ~mem_full;
   assign data_req_o.q.write = lsu_qwrite_i;
   assign data_req_o.q.addr = lsu_qaddr_i;
+  assign data_req_o.q.mask = lsu_qmcast_i;
   assign data_req_o.q.amo  = lsu_qamo_i;
   assign data_req_o.q.size = lsu_qsize_i;
 

hw/snitch_cluster/src/snitch_cluster.sv

@@ -38,6 +38,8 @@ module snitch_cluster
   parameter int unsigned NarrowUserWidth    = 1,
   /// AXI: dma user width.
   parameter int unsigned WideUserWidth      = 1,
+  /// Width of the atomic ID to be used in a system.
+  parameter int unsigned AtomicIdWidth      = 1,
   /// Boot Address from which to fetch the first instructions.
   /// Used if `AliasRegionEnable` or `IntBootromEnable` is not set.
   parameter logic [31:0] BootAddr           = 32'h0,
@@ -71,6 +73,8 @@ module snitch_cluster
   parameter int unsigned ICacheWays [NrHives]      = '{default: 0},
   /// Enable virtual memory support.
   parameter bit          VMSupport          = 1,
+  /// Enable multicast on DMA XBAR.
+  parameter bit          EnableDMAMulticast = 0,
   /// Per-core enabling of the standard `E` ISA reduced-register extension.
   parameter bit [NrCores-1:0] RVE           = '0,
   /// Per-core enabling of the standard `F` ISA extensions.
@@ -307,10 +311,29 @@ module snitch_cluster
     UniqueIds: 1'b0,
     AxiAddrWidth: PhysicalAddrWidth,
     AxiDataWidth: NarrowDataWidth,
-    NoAddrRules: NrRules
+    NoAddrRules: NrRules,
+    default: '0
   };
 
   // DMA configuration struct
+  localparam axi_pkg::xbar_cfg_t DmaMcastXbarCfg = '{
+    NoSlvPorts: NrWideMasters,
+    NoMstPorts: NrWideSlaves,
+    MaxMstTrans: WideMaxMstTrans,
+    MaxSlvTrans: WideMaxSlvTrans,
+    FallThrough: 1'b0,
+    LatencyMode: WideXbarLatency,
+    PipelineStages: 0,
+    AxiIdWidthSlvPorts: WideIdWidthIn,
+    AxiIdUsedSlvPorts: WideIdWidthIn,
+    UniqueIds: 1'b0,
+    AxiAddrWidth: PhysicalAddrWidth,
+    AxiDataWidth: WideDataWidth,
+    NoAddrRules: NrWideRules,
+    NoMulticastRules: 1,
+    NoMulticastPorts: 2,
+    default: '0
+  };
   localparam axi_pkg::xbar_cfg_t DmaXbarCfg = '{
     NoSlvPorts: NrWideMasters,
     NoMstPorts: NrWideSlaves,
@@ -324,7 +347,8 @@ module snitch_cluster
     UniqueIds: 1'b0,
     AxiAddrWidth: PhysicalAddrWidth,
     AxiDataWidth: WideDataWidth,
-    NoAddrRules: NrWideRules
+    NoAddrRules: NrWideRules,
+    default: '0
   };
 
   function automatic int unsigned get_hive_size(int unsigned current_hive);
@@ -355,7 +379,9 @@ module snitch_cluster
   typedef logic [WideIdWidthIn-1:0]     id_dma_mst_t;
   typedef logic [WideIdWidthOut-1:0]    id_dma_slv_t;
   typedef logic [NarrowUserWidth-1:0]   user_t;
-  typedef logic [WideUserWidth-1:0]     user_dma_t;
+  typedef struct packed {
+    logic [WideUserWidth-1:0] mcast;
+  } user_dma_t;
 
   typedef logic [TCDMMemAddrWidth-1:0]  tcdm_mem_addr_t;
   typedef logic [TCDMAddrWidth-1:0]     tcdm_addr_t;
@@ -587,8 +613,14 @@ module snitch_cluster
     .mst_resp_i (wide_axi_mst_rsp[SoCDMAIn])
   );
 
-  logic [DmaXbarCfg.NoSlvPorts-1:0][$clog2(DmaXbarCfg.NoMstPorts)-1:0] dma_xbar_default_port;
-  assign dma_xbar_default_port = '{default: SoCDMAOut};
+
+  int unsigned dma_xbar_default_port = SoCDMAOut;
+  xbar_rule_t dma_xbar_default_port_rule;
+  assign dma_xbar_default_port_rule = '{
+    idx: dma_xbar_default_port,
+    start_addr: tcdm_start_address,
+    end_addr: zero_mem_end_address
+  };
 
   xbar_rule_t [5:0] dma_xbar_rules;
   xbar_rule_t [DmaXbarCfg.NoAddrRules-1:0] enabled_dma_xbar_rule;
@@ -615,35 +647,67 @@ module snitch_cluster
   end
 
   localparam bit [DmaXbarCfg.NoSlvPorts-1:0] DMAEnableDefaultMstPort = '1;
-  axi_xbar #(
-    .Cfg (DmaXbarCfg),
-    .ATOPs (0),
-    .slv_aw_chan_t (axi_mst_dma_aw_chan_t),
-    .mst_aw_chan_t (axi_slv_dma_aw_chan_t),
-    .w_chan_t (axi_mst_dma_w_chan_t),
-    .slv_b_chan_t (axi_mst_dma_b_chan_t),
-    .mst_b_chan_t (axi_slv_dma_b_chan_t),
-    .slv_ar_chan_t (axi_mst_dma_ar_chan_t),
-    .mst_ar_chan_t (axi_slv_dma_ar_chan_t),
-    .slv_r_chan_t (axi_mst_dma_r_chan_t),
-    .mst_r_chan_t (axi_slv_dma_r_chan_t),
-    .slv_req_t (axi_mst_dma_req_t),
-    .slv_resp_t (axi_mst_dma_resp_t),
-    .mst_req_t (axi_slv_dma_req_t),
-    .mst_resp_t (axi_slv_dma_resp_t),
-    .rule_t (xbar_rule_t)
-  ) i_axi_dma_xbar (
-    .clk_i (clk_i),
-    .rst_ni (rst_ni),
-    .test_i (1'b0),
-    .slv_ports_req_i (wide_axi_mst_req),
-    .slv_ports_resp_o (wide_axi_mst_rsp),
-    .mst_ports_req_o (wide_axi_slv_req),
-    .mst_ports_resp_i (wide_axi_slv_rsp),
-    .addr_map_i (enabled_dma_xbar_rule),
-    .en_default_mst_port_i (DMAEnableDefaultMstPort),
-    .default_mst_port_i (dma_xbar_default_port)
-  );
+  if (EnableDMAMulticast) begin : gen_mcast_dma_xbar
+    axi_mcast_xbar #(
+      .Cfg (DmaMcastXbarCfg),
+      .ATOPs (0),
+      .slv_aw_chan_t (axi_mst_dma_aw_chan_t),
+      .mst_aw_chan_t (axi_slv_dma_aw_chan_t),
+      .w_chan_t (axi_mst_dma_w_chan_t),
+      .slv_b_chan_t (axi_mst_dma_b_chan_t),
+      .mst_b_chan_t (axi_slv_dma_b_chan_t),
+      .slv_ar_chan_t (axi_mst_dma_ar_chan_t),
+      .mst_ar_chan_t (axi_slv_dma_ar_chan_t),
+      .slv_r_chan_t (axi_mst_dma_r_chan_t),
+      .mst_r_chan_t (axi_slv_dma_r_chan_t),
+      .slv_req_t (axi_mst_dma_req_t),
+      .slv_resp_t (axi_mst_dma_resp_t),
+      .mst_req_t (axi_slv_dma_req_t),
+      .mst_resp_t (axi_slv_dma_resp_t),
+      .rule_t (xbar_rule_t)
+    ) i_axi_dma_xbar (
+      .clk_i (clk_i),
+      .rst_ni (rst_ni),
+      .test_i (1'b0),
+      .slv_ports_req_i (wide_axi_mst_req),
+      .slv_ports_resp_o (wide_axi_mst_rsp),
+      .mst_ports_req_o (wide_axi_slv_req),
+      .mst_ports_resp_i (wide_axi_slv_rsp),
+      .addr_map_i (enabled_dma_xbar_rule),
+      .en_default_mst_port_i (DMAEnableDefaultMstPort),
+      .default_mst_port_i ({DmaXbarCfg.NoSlvPorts{dma_xbar_default_port_rule}})
+    );
+  end else begin : gen_dma_xbar
+    axi_xbar #(
+      .Cfg (DmaXbarCfg),
+      .ATOPs (0),
+      .slv_aw_chan_t (axi_mst_dma_aw_chan_t),
+      .mst_aw_chan_t (axi_slv_dma_aw_chan_t),
+      .w_chan_t (axi_mst_dma_w_chan_t),
+      .slv_b_chan_t (axi_mst_dma_b_chan_t),
+      .mst_b_chan_t (axi_slv_dma_b_chan_t),
+      .slv_ar_chan_t (axi_mst_dma_ar_chan_t),
+      .mst_ar_chan_t (axi_slv_dma_ar_chan_t),
+      .slv_r_chan_t (axi_mst_dma_r_chan_t),
+      .mst_r_chan_t (axi_slv_dma_r_chan_t),
+      .slv_req_t (axi_mst_dma_req_t),
+      .slv_resp_t (axi_mst_dma_resp_t),
+      .mst_req_t (axi_slv_dma_req_t),
+      .mst_resp_t (axi_slv_dma_resp_t),
+      .rule_t (xbar_rule_t)
+    ) i_axi_dma_xbar (
+      .clk_i (clk_i),
+      .rst_ni (rst_ni),
+      .test_i (1'b0),
+      .slv_ports_req_i (wide_axi_mst_req),
+      .slv_ports_resp_o (wide_axi_mst_rsp),
+      .mst_ports_req_o (wide_axi_slv_req),
+      .mst_ports_resp_i (wide_axi_slv_rsp),
+      .addr_map_i (enabled_dma_xbar_rule),
+      .en_default_mst_port_i (DMAEnableDefaultMstPort),
+      .default_mst_port_i ({DmaXbarCfg.NoSlvPorts{dma_xbar_default_port}})
+    );
+  end
 
   axi_zero_mem #(
     .axi_req_t (axi_slv_dma_req_t),
@@ -1089,7 +1153,8 @@ module snitch_cluster
   user_t cluster_user;
   // Atomic ID, needs to be unique ID of cluster
   // cluster_id + HartIdOffset + 1 (because 0 is for non-atomic masters)
-  assign cluster_user = (hart_base_id_i / NrCores) +  (hart_base_id_i % NrCores) + 1'b1;
+  assign cluster_user = (core_to_axi_req.q.mask << AtomicIdWidth) |
+                        ((hart_base_id_i / NrCores) +  (hart_base_id_i % NrCores) + 1'b1);
 
   reqrsp_mux #(
     .NrPorts (NrCores),

hw/snitch_cluster/src/snitch_cluster_pkg.sv.tpl

@@ -58,6 +58,7 @@ package ${cfg['cluster']['name']}_pkg;
 
   localparam int unsigned NarrowUserWidth = ${cfg['cluster']['user_width']};
   localparam int unsigned WideUserWidth = ${cfg['cluster']['dma_user_width']};
+  localparam int unsigned AtomicIdWidth = ${cfg['cluster']['atomic_id_width']};
 
   localparam int unsigned ICacheLineWidth [NrHives] = '{${icache_cfg('cacheline')}};
   localparam int unsigned ICacheLineCount [NrHives] = '{${icache_cfg('depth')}};