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hw: Mask TCDM write data stability check on reads
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+29
-3
lines changed

2 files changed

+29
-3
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Bender.local

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Original file line numberDiff line numberDiff line change
@@ -5,3 +5,5 @@
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overrides:
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# Some of our dependencies have false conflicts with our new AXI version; force our version.
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axi: {git: https://github.com/pulp-platform/axi.git, version: 0.39.0}
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# TODO: remove after common_cells merge and release
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common_cells: {git: https://github.com/pulp-platform/common_cells.git, rev: paulsc/xbar-stab-mask}

hw/snitch_cluster/src/snitch_tcdm_interconnect.sv

Lines changed: 27 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,12 @@ module snitch_tcdm_interconnect #(
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typedef logic [StrbWidth-1:0] strb_t;
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`MEM_TYPEDEF_REQ_CHAN_T(mem_req_chan_t, addr_t, data_t, strb_t, user_t);
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// Do not assert unconditional stability on write data inside interconnects,
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// as write data may freely change on (non-atomic) reads. We properly assert
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// conditional write data stability below.
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localparam mem_req_chan_t MemReqAsrtMask =
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'{data: '0, strb: '0, amo: reqrsp_pkg::amo_op_e'('1), default: '1};
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// Width of the bank select signal.
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localparam int unsigned SelWidth = cf_math_pkg::idx_width(NumOut);
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typedef logic [SelWidth-1:0] select_t;
@@ -88,7 +94,7 @@ module snitch_tcdm_interconnect #(
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logic [NumInp-1:0] req_q_valid_flat, rsp_q_ready_flat;
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logic [NumOut-1:0] mem_q_valid_flat, mem_q_ready_flat;
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91-
// The usual struct packing unpacking.
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// The usual struct packing unpacking; also check write stability here.
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for (genvar i = 0; i < NumInp; i++) begin : gen_flat_inp
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assign req_q_valid_flat[i] = req_i[i].q_valid;
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assign rsp_o[i].q_ready = rsp_q_ready_flat[i];
@@ -100,6 +106,22 @@ module snitch_tcdm_interconnect #(
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strb: req_i[i].q.strb,
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user: req_i[i].q.user
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};
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// Write data must also be stable during AMOs, so include this case in assertions.
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logic in_req_alters_mem;
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assign in_req_alters_mem = in_req[i].write | (in_req[i].amo != reqrsp_pkg::AMONone);
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// TODO: we could clean this up with an additional common_cells assertion macro.
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`ifndef VERILATOR
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`ifndef SYNTHESIS
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assert property (@(posedge clk_i) disable iff (~rst_ni) (req_q_valid_flat[i] &&
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!rsp_q_ready_flat[i] && in_req_alters_mem |=> $stable(in_req[i].data))) else
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$error("write data during non-read is unstable at input: %0d", i);
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assert property (@(posedge clk_i) disable iff (~rst_ni) (req_q_valid_flat[i] &&
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!rsp_q_ready_flat[i] && in_req_alters_mem |=> $stable(in_req[i].strb))) else
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$error("write strobe during non-read is unstable at input: %0d", i);
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`endif
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`endif
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end
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for (genvar i = 0; i < NumOut; i++) begin : gen_flat_oup
@@ -121,7 +143,8 @@ module snitch_tcdm_interconnect #(
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.OutSpillReg ( 1'b0 ),
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.ExtPrio ( 1'b0 ),
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.AxiVldRdy ( 1'b1 ),
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.LockIn ( 1'b1 )
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.LockIn ( 1'b1 ),
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.AxiVldMask ( MemReqAsrtMask )
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) i_stream_xbar (
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.clk_i,
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.rst_ni,
@@ -198,7 +221,8 @@ module snitch_tcdm_interconnect #(
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.SpillReg ( 1'b0 ),
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.AxiVldRdy ( 1'b1 ),
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.LockIn ( 1'b1 ),
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.Radix ( Radix )
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.Radix ( Radix ),
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.AxiVldMask ( MemReqAsrtMask )
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) i_stream_omega_net (
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.clk_i,
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.rst_ni,

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