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fischeticolluca
fischeti
and
colluca
authored
clustergen: Improvements for generation with templates (#202)
Co-authored-by: Luca Colagrande <luca.colagrande3@gmail.com>
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-1015
lines changed

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+934
-1015
lines changed

‎.github/workflows/ci.yml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -113,11 +113,11 @@ jobs:
113113
if: steps.verilator-cache.outputs.cache-hit != 'true'
114114
working-directory: target/snitch_cluster
115115
run: |
116-
make CFG_OVERRIDE=cfg/github-ci.hjson VLT_JOBS=1 bin/snitch_cluster.vlt
116+
make CFG_OVERRIDE=cfg/github-ci.json VLT_JOBS=1 bin/snitch_cluster.vlt
117117
- name: Build Software
118118
working-directory: target/snitch_cluster
119119
run: |
120-
make CFG_OVERRIDE=cfg/github-ci.hjson sw
120+
make CFG_OVERRIDE=cfg/github-ci.json sw
121121
- name: Run Tests
122122
working-directory: target/snitch_cluster
123123
run: |

‎.gitlab-ci.yml

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ snitch-cluster-banshee:
132132
snitch-cluster-fdiv-vsim:
133133
script:
134134
- cd target/snitch_cluster
135-
- make CFG_OVERRIDE=cfg/fdiv.hjson sw
135+
- make CFG_OVERRIDE=cfg/fdiv.json sw
136136
- make bin/snitch_cluster.vsim
137137
- ./util/run.py sw/fdiv.yaml --simulator vsim -j --run-dir runs/vsim
138138
# Run additional, more extensive tests
@@ -142,15 +142,15 @@ snitch-cluster-fdiv-vsim:
142142
snitch-cluster-omega-vsim:
143143
script:
144144
- cd target/snitch_cluster
145-
- make CFG_OVERRIDE=cfg/omega.hjson sw
145+
- make CFG_OVERRIDE=cfg/omega.json sw
146146
- make bin/snitch_cluster.vsim
147147
- ./util/run.py sw/run.yaml --simulator vsim -j --run-dir runs/vsim
148148

149149
# Test Multi-channel DMA
150150
snitch-cluster-mchan-vsim:
151151
script:
152152
- cd target/snitch_cluster
153-
- make CFG_OVERRIDE=cfg/dma_mchan.hjson sw
153+
- make CFG_OVERRIDE=cfg/dma_mchan.json sw
154154
- make bin/snitch_cluster.vsim
155155
- ./util/run.py sw/dma_mchan.yaml --simulator vsim -j --run-dir runs/vsim
156156

‎hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl

Lines changed: 151 additions & 147 deletions
Large diffs are not rendered by default.

‎hw/snitch_cluster/test/bootdata.cc.tpl

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,9 +12,9 @@ const BootData BOOTDATA = {.boot_addr = ${hex(cfg['cluster']['boot_addr'])},
1212
.tcdm_start = ${hex(cfg['cluster']['cluster_base_addr'])},
1313
.tcdm_size = ${hex(cfg['cluster']['tcdm']['size'] * 1024)},
1414
.tcdm_offset = ${hex(cfg['cluster']['cluster_base_offset'])},
15-
.global_mem_start = ${hex(cfg['dram']['address'])},
16-
.global_mem_end = ${hex(cfg['dram']['address'] + cfg['dram']['length'])},
15+
.global_mem_start = ${hex(next(reg['address'] for reg in cfg['external_addr_regions'] if reg['name'] == 'dram'))},
16+
.global_mem_end = ${hex(next(reg['address'] + reg['length'] for reg in cfg['external_addr_regions'] if reg['name'] == 'dram'))},
1717
.cluster_count = ${cfg['nr_clusters']},
18-
.clint_base = ${hex(cfg['peripherals']['clint']['address'])}};
18+
.clint_base = ${hex(next(reg['address'] + reg['length'] for reg in cfg['external_addr_regions'] if reg['name'] == 'clint'))}};
1919

2020
} // namespace sim

‎hw/snitch_cluster/test/link.ld.tpl

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,12 @@
44

55
OUTPUT_ARCH( "riscv" )
66
ENTRY(_start)
7-
<% dram_address = cfg['dram']['address']; %>
7+
<% dram_address = next(reg['address'] for reg in cfg['external_addr_regions'] if reg['name'] == 'dram'); %>
8+
<% dram_length = next(reg['length'] for reg in cfg['external_addr_regions'] if reg['name'] == 'dram'); %>
9+
810
MEMORY
911
{
10-
DRAM (rwxai) : ORIGIN = ${dram_address}, LENGTH = ${cfg['dram']['length']}
12+
DRAM (rwxai) : ORIGIN = ${dram_address}, LENGTH = ${dram_length}
1113
L1 (rw) : ORIGIN = ${l1_region[0]}, LENGTH = ${l1_region[1]}K
1214
}
1315

‎pyproject.toml

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@ dependencies = [
1919
"editorconfig-checker==2.3.51",
2020
"flake8",
2121
"gitpython",
22-
"hjson",
2322
"humanize",
2423
"json5",
2524
"jsonref",

‎target/common/common.mk

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -193,6 +193,15 @@ define BINARY_SIZE_CHECK
193193
@[ "$$(stat -c %s $(1))" -lt "$(2)" ] || (echo "Binary exceeds specified size of $(2)B"; exit 1)
194194
endef
195195

196+
# Common rule to fill a template file with clustergen
197+
# Arg 1: path for the generated file
198+
# Arg 2: path of the template file
199+
define cluster_gen_rule
200+
$(1): $(CFG) $(CLUSTER_GEN_PREREQ) $(2) | $(GENERATED_DIR)
201+
@echo "[CLUSTERGEN] Generate $$@"
202+
$(CLUSTER_GEN) -c $$< -o $$@ --template $(2)
203+
endef
204+
196205
##########
197206
# Traces #
198207
##########

‎target/snitch_cluster/.gitignore

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/logs/
22
/generated/
33
/bin/
4-
/cfg/lru.hjson
4+
/cfg/lru.json
55
/work/
66
/work-vsim/
77
/work-vlt/

‎target/snitch_cluster/Makefile

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -56,8 +56,8 @@ PERIPH_DIR ?= $(ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral
5656
# (LRU) config, all targets depending on the configuration file have
5757
# to be rebuilt. This file is used to express this condition as a
5858
# prerequisite for other rules.
59-
DEFAULT_CFG = cfg/default.hjson
60-
CFG = cfg/lru.hjson
59+
DEFAULT_CFG = cfg/default.json
60+
CFG = cfg/lru.json
6161

6262
# Common dependency for all RTL simulators
6363
$(BIN_DIR):
@@ -161,17 +161,14 @@ clean-rtl:
161161
$(GENERATED_DIR):
162162
mkdir -p $@
163163

164-
$(GENERATED_DIR)/snitch_cluster_wrapper.sv: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR)
165-
$(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --wrapper
164+
CLUSTER_GEN_TPL = $(ROOT)/hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl
165+
LINK_LD_TPL = $(ROOT)/hw/snitch_cluster/test/link.ld.tpl
166+
BOOTDATA_TPL = $(ROOT)/hw/snitch_cluster/test/bootdata.cc.tpl
166167

167-
$(GENERATED_DIR)/link.ld: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR)
168-
$(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --linker
169-
170-
$(GENERATED_DIR)/memories.json: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR)
171-
$(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --memories
172-
173-
$(GENERATED_DIR)/bootdata.cc: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR)
174-
$(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --bootdata
168+
# OCCAMYGEN artifacts
169+
$(eval $(call cluster_gen_rule,$(GENERATED_DIR)/snitch_cluster_wrapper.sv,$(CLUSTER_GEN_TPL)))
170+
$(eval $(call cluster_gen_rule,$(GENERATED_DIR)/link.ld,$(LINK_LD_TPL)))
171+
$(eval $(call cluster_gen_rule,$(GENERATED_DIR)/bootdata.cc,$(BOOTDATA_TPL)))
175172

176173
# REGGEN regfile
177174
$(PERIPH_DIR)/snitch_cluster_peripheral_reg_pkg.sv: $(PERIPH_DIR)/snitch_cluster_peripheral_reg_top.sv

‎target/snitch_cluster/cfg/default.hjson renamed to ‎target/snitch_cluster/cfg/default.json

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
// Cluster configuration for a simple testbench system.
66
{
77
cluster: {
8-
cluster_base_addr: 268435456, // 0x1000_0000
9-
cluster_base_offset: 0, // 0x0
8+
cluster_base_addr: 0x10000000,
9+
cluster_base_offset: 0,
1010
cluster_base_hartid: 0,
1111
addr_width: 48,
1212
data_width: 64,
@@ -80,20 +80,19 @@
8080
}
8181
]
8282
},
83-
dram: {
84-
// 0x8000_0000
85-
address: 2147483648,
86-
// 0x8000_0000
87-
length: 2147483648
88-
},
89-
peripherals: {
90-
clint: {
91-
// 0xffff_0000
92-
address: 4294901760,
93-
// 0x0000_1000
94-
length: 4096
83+
external_addr_regions: [
84+
{
85+
name: "dram",
86+
address: 0x80000000,
87+
length: 0x80000000,
88+
cacheable: true
9589
},
96-
},
90+
{
91+
name: "clint",
92+
address: 0xFFFF0000,
93+
length: 0x1000
94+
},
95+
],
9796
// Templates.
9897
compute_core_template: {
9998
isa: "rv32imafd",

‎target/snitch_cluster/cfg/dma_mchan.hjson renamed to ‎target/snitch_cluster/cfg/dma_mchan.json

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
// Cluster configuration for a simple testbench system.
66
{
77
cluster: {
8-
cluster_base_addr: 268435456, // 0x1000_0000
9-
cluster_base_offset: 0, // 0x0
8+
cluster_base_addr: 0x10000000,
9+
cluster_base_offset: 0,
1010
cluster_base_hartid: 0,
1111
addr_width: 48,
1212
data_width: 64,
@@ -81,20 +81,19 @@
8181
}
8282
]
8383
},
84-
dram: {
85-
// 0x8000_0000
86-
address: 2147483648,
87-
// 0x8000_0000
88-
length: 2147483648
89-
},
90-
peripherals: {
91-
clint: {
92-
// 0xffff_0000
93-
address: 4294901760,
94-
// 0x0000_1000
95-
length: 4096
84+
external_addr_regions: [
85+
{
86+
name: "dram",
87+
address: 0x80000000,
88+
length: 0x80000000,
89+
cacheable: true
9690
},
97-
},
91+
{
92+
name: "clint",
93+
address: 0xFFFF0000,
94+
length: 0x1000
95+
},
96+
],
9897
// Templates.
9998
compute_core_template: {
10099
isa: "rv32imafd",

‎target/snitch_cluster/cfg/fdiv.hjson renamed to ‎target/snitch_cluster/cfg/fdiv.json

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
// Cluster configuration for a simple testbench system.
66
{
77
cluster: {
8-
cluster_base_addr: 268435456, // 0x1000_0000
9-
cluster_base_offset: 0, // 0x0
8+
cluster_base_addr: 0x10000000,
9+
cluster_base_offset: 0,
1010
cluster_base_hartid: 0,
1111
addr_width: 48,
1212
data_width: 64,
@@ -80,20 +80,19 @@
8080
}
8181
]
8282
},
83-
dram: {
84-
// 0x8000_0000
85-
address: 2147483648,
86-
// 0x8000_0000
87-
length: 2147483648
88-
},
89-
peripherals: {
90-
clint: {
91-
// 0xffff_0000
92-
address: 4294901760,
93-
// 0x0000_1000
94-
length: 4096
83+
external_addr_regions: [
84+
{
85+
name: "dram",
86+
address: 0x80000000,
87+
length: 0x80000000,
88+
cacheable: true
9589
},
96-
},
90+
{
91+
name: "clint",
92+
address: 0xFFFF0000,
93+
length: 0x1000
94+
},
95+
],
9796
// Templates.
9897
compute_core_template: {
9998
isa: "rv32imafd",

‎target/snitch_cluster/cfg/github-ci.hjson renamed to ‎target/snitch_cluster/cfg/github-ci.json

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
// Cluster configuration for a simple testbench system.
66
{
77
cluster: {
8-
cluster_base_addr: 268435456, // 0x1000_0000
9-
cluster_base_offset: 0, // 0x0
8+
cluster_base_addr: 0x10000000,
9+
cluster_base_offset: 0,
1010
cluster_base_hartid: 0,
1111
addr_width: 48,
1212
data_width: 64,
@@ -76,20 +76,19 @@
7676
}
7777
]
7878
},
79-
dram: {
80-
// 0x8000_0000
81-
address: 2147483648,
82-
// 0x8000_0000
83-
length: 2147483648
84-
},
85-
peripherals: {
86-
clint: {
87-
// 0xffff_0000
88-
address: 4294901760,
89-
// 0x0000_1000
90-
length: 4096
79+
external_addr_regions: [
80+
{
81+
name: "dram",
82+
address: 0x80000000,
83+
length: 0x80000000,
84+
cacheable: true
9185
},
92-
},
86+
{
87+
name: "clint",
88+
address: 0xFFFF0000,
89+
length: 0x1000
90+
},
91+
],
9392
// Templates.
9493
compute_core_template: {
9594
isa: "rv32imafd",

‎target/snitch_cluster/cfg/omega.hjson renamed to ‎target/snitch_cluster/cfg/omega.json

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -5,16 +5,16 @@
55
// Cluster configuration for a simple testbench system.
66
{
77
cluster: {
8-
cluster_base_addr: 268435456, // 0x1000_0000
9-
cluster_base_offset: 0, // 0x0
8+
cluster_base_addr: 0x10000000,
9+
cluster_base_offset: 0,
1010
cluster_base_hartid: 0,
1111
addr_width: 48,
1212
data_width: 64,
1313
user_width: 5, // clog2(total number of clusters)
1414
tcdm: {
1515
size: 128,
1616
banks: 32,
17-
topology: OmegaNet
17+
topology: 'OmegaNet'
1818
},
1919
cluster_periph_size: 60, // kB
2020
zero_mem_size: 64, // kB
@@ -81,20 +81,19 @@
8181
}
8282
]
8383
},
84-
dram: {
85-
// 0x8000_0000
86-
address: 2147483648,
87-
// 0x8000_0000
88-
length: 2147483648
89-
},
90-
peripherals: {
91-
clint: {
92-
// 0xffff_0000
93-
address: 4294901760,
94-
// 0x0000_1000
95-
length: 4096
84+
external_addr_regions: [
85+
{
86+
name: "dram",
87+
address: 0x80000000,
88+
length: 0x80000000,
89+
cacheable: true
9690
},
97-
},
91+
{
92+
name: "clint",
93+
address: 0xFFFF0000,
94+
length: 0x1000
95+
},
96+
],
9897
// Templates.
9998
compute_core_template: {
10099
isa: "rv32imafd",

‎target/snitch_cluster/sw.mk

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -17,21 +17,20 @@ clean: clean-sw
1717
# Platform headers #
1818
####################
1919

20-
CLUSTER_GEN_HEADERS = snitch_cluster_cfg.h \
21-
snitch_cluster_addrmap.h
20+
TARGET_C_HDRS_DIR = $(ROOT)/target/snitch_cluster/sw/runtime/common
2221

23-
REGGEN_HEADERS = snitch_cluster_peripheral.h
22+
SNITCH_CLUSTER_CFG_H = $(TARGET_C_HDRS_DIR)/snitch_cluster_cfg.h
23+
SNITCH_CLUSTER_ADDRMAP_H = $(TARGET_C_HDRS_DIR)/snitch_cluster_addrmap.h
24+
SNITCH_CLUSTER_PERIPHERAL_H = $(TARGET_C_HDRS_DIR)/snitch_cluster_peripheral.h
2425

25-
TARGET_C_HDRS_DIR = $(ROOT)/target/snitch_cluster/sw/runtime/common
26-
TARGET_C_HDRS = $(addprefix $(TARGET_C_HDRS_DIR)/,$(CLUSTER_GEN_HEADERS) $(REGGEN_HEADERS))
26+
TARGET_C_HDRS = $(SNITCH_CLUSTER_CFG_H) $(SNITCH_CLUSTER_ADDRMAP_H) $(SNITCH_CLUSTER_PERIPHERAL_H)
2727

28-
# CLUSTERGEN headers,
29-
$(addprefix $(TARGET_C_HDRS_DIR)/,$(CLUSTER_GEN_HEADERS)): %.h: $(CFG) $(CLUSTER_GEN_PREREQ) %.h.tpl
30-
@echo "[CLUSTERGEN] Generate $@"
31-
$(CLUSTER_GEN) -c $< --outdir $(TARGET_C_HDRS_DIR) --template $@.tpl
28+
# CLUSTERGEN headers
29+
$(eval $(call cluster_gen_rule,$(SNITCH_CLUSTER_CFG_H),$(SNITCH_CLUSTER_CFG_H).tpl))
30+
$(eval $(call cluster_gen_rule,$(SNITCH_CLUSTER_ADDRMAP_H),$(SNITCH_CLUSTER_ADDRMAP_H).tpl))
3231

3332
# REGGEN headers
34-
$(TARGET_C_HDRS_DIR)/snitch_cluster_peripheral.h: $(ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson $(REGGEN)
33+
$(SNITCH_CLUSTER_PERIPHERAL_H): $(ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson $(REGGEN)
3534
$(call reggen_generate_header,$@,$<)
3635

3736
.PHONY: clean-headers

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