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Small changes to fix RTL build flow.
1 parent a35ba18 commit ca66852

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-2
lines changed

2 files changed

+2
-2
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target/common/common.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ MATCH_BGN := 's/+incdir+//g'
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MATCH_DEF := '/+define+/d'
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SED_SRCS := sed -e ${MATCH_END} -e ${MATCH_BGN} -e ${MATCH_DEF}
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COMMON_BENDER_FLAGS += -t rtl
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COMMON_BENDER_FLAGS += -t rtl -t snitch_cluster
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COMMON_SIM_BENDER_FLAGS += -t simulation -t test
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# fesvr is being installed here

target/common/vsim.mk

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ $(VSIM_BUILDDIR)/compile.vsim.tcl: $(BENDER_LOCK) | $(VSIM_BUILDDIR)
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$(BIN_DIR)/$(TARGET).vsim: $(VSIM_BUILDDIR)/compile.vsim.tcl $(VSIM_SOURCES) $(TB_SRCS) $(TB_CC_SOURCES) $(RTL_CC_SOURCES) work/lib/libfesvr.a | $(BIN_DIR)
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$(VSIM) -c -do "source $<; quit" | tee $(VSIM_BUILDDIR)vlog.log
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@! grep -P "Errors: [1-9]*," $(VSIM_BUILDDIR)vlog.log
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$(VOPT) $(VOPT_FLAGS) tb_bin -o tb_bin_opt | tee $(VSIM_BUILDDIR)vopt.log
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$(VOPT) $(VOPT_FLAGS) -work $(VSIM_BUILDDIR) tb_bin -o tb_bin_opt | tee $(VSIM_BUILDDIR)vopt.log
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@! grep -P "Errors: [1-9]*," $(VSIM_BUILDDIR)vopt.log
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@echo "#!/bin/bash" > $@
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@echo 'binary=$$(realpath $$1)' >> $@

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