clustergen: Improvements for generation with templates

.github/workflows/ci.yml

@@ -113,11 +113,11 @@ jobs:
         if: steps.verilator-cache.outputs.cache-hit != 'true'
         working-directory: target/snitch_cluster
         run: |
-          make CFG_OVERRIDE=cfg/github-ci.hjson VLT_JOBS=1 bin/snitch_cluster.vlt
+          make CFG_OVERRIDE=cfg/github-ci.json VLT_JOBS=1 bin/snitch_cluster.vlt
       - name: Build Software
         working-directory: target/snitch_cluster
         run: |
-          make CFG_OVERRIDE=cfg/github-ci.hjson sw
+          make CFG_OVERRIDE=cfg/github-ci.json sw
       - name: Run Tests
         working-directory: target/snitch_cluster
         run: |

.gitlab-ci.yml

@@ -132,7 +132,7 @@ snitch-cluster-banshee:
 snitch-cluster-fdiv-vsim:
   script:
     - cd target/snitch_cluster
-    - make CFG_OVERRIDE=cfg/fdiv.hjson sw
+    - make CFG_OVERRIDE=cfg/fdiv.json sw
     - make bin/snitch_cluster.vsim
     - ./util/run.py sw/fdiv.yaml --simulator vsim -j --run-dir runs/vsim
     # Run additional, more extensive tests
@@ -142,15 +142,15 @@ snitch-cluster-fdiv-vsim:
 snitch-cluster-omega-vsim:
   script:
     - cd target/snitch_cluster
-    - make CFG_OVERRIDE=cfg/omega.hjson sw
+    - make CFG_OVERRIDE=cfg/omega.json sw
     - make bin/snitch_cluster.vsim
     - ./util/run.py sw/run.yaml --simulator vsim -j --run-dir runs/vsim
 
 # Test Multi-channel DMA
 snitch-cluster-mchan-vsim:
   script:
     - cd target/snitch_cluster
-    - make CFG_OVERRIDE=cfg/dma_mchan.hjson sw
+    - make CFG_OVERRIDE=cfg/dma_mchan.json sw
     - make bin/snitch_cluster.vsim
     - ./util/run.py sw/dma_mchan.yaml --simulator vsim -j --run-dir runs/vsim
 

hw/snitch_cluster/test/bootdata.cc.tpl

@@ -12,9 +12,9 @@ const BootData BOOTDATA = {.boot_addr = ${hex(cfg['cluster']['boot_addr'])},
                            .tcdm_start = ${hex(cfg['cluster']['cluster_base_addr'])},
                            .tcdm_size = ${hex(cfg['cluster']['tcdm']['size'] * 1024)},
                            .tcdm_offset = ${hex(cfg['cluster']['cluster_base_offset'])},
-                           .global_mem_start = ${hex(cfg['dram']['address'])},
-                           .global_mem_end = ${hex(cfg['dram']['address'] + cfg['dram']['length'])},
+                           .global_mem_start = ${hex(next(reg['address'] for reg in cfg['external_addr_regions'] if reg['name'] == 'dram'))},
+                           .global_mem_end = ${hex(next(reg['address'] + reg['length'] for reg in cfg['external_addr_regions'] if reg['name'] == 'dram'))},
                            .cluster_count = ${cfg['nr_clusters']},
-                           .clint_base = ${hex(cfg['peripherals']['clint']['address'])}};
+                           .clint_base = ${hex(next(reg['address'] + reg['length'] for reg in cfg['external_addr_regions'] if reg['name'] == 'clint'))}};
 
 }  // namespace sim

hw/snitch_cluster/test/link.ld.tpl

@@ -4,10 +4,12 @@
 
 OUTPUT_ARCH( "riscv" )
 ENTRY(_start)
-<% dram_address = cfg['dram']['address']; %>
+<% dram_address = next(reg['address'] for reg in cfg['external_addr_regions'] if reg['name'] == 'dram'); %>
+<% dram_length = next(reg['length'] for reg in cfg['external_addr_regions'] if reg['name'] == 'dram'); %>
+
 MEMORY
 {
-    DRAM (rwxai)  : ORIGIN = ${dram_address}, LENGTH = ${cfg['dram']['length']}
+    DRAM (rwxai)  : ORIGIN = ${dram_address}, LENGTH = ${dram_length}
     L1 (rw) : ORIGIN = ${l1_region[0]}, LENGTH = ${l1_region[1]}K
 }
 

pyproject.toml

@@ -19,7 +19,6 @@ dependencies = [
     "editorconfig-checker==2.3.51",
     "flake8",
     "gitpython",
-    "hjson",
     "humanize",
     "json5",
     "jsonref",

target/common/common.mk

@@ -193,6 +193,15 @@ define BINARY_SIZE_CHECK
   @[ "$$(stat -c %s $(1))" -lt "$(2)" ] || (echo "Binary exceeds specified size of $(2)B"; exit 1)
 endef
 
+# Common rule to fill a template file with clustergen
+# Arg 1: path for the generated file
+# Arg 2: path of the template file
+define cluster_gen_rule
+$(1): $(CFG) $(CLUSTER_GEN_PREREQ) $(2) | $(GENERATED_DIR)
+	@echo "[CLUSTERGEN] Generate $$@"
+	$(CLUSTER_GEN) -c $$< -o $$@ --template $(2)
+endef
+
 ##########
 # Traces #
 ##########

target/snitch_cluster/.gitignore

@@ -1,7 +1,7 @@
 /logs/
 /generated/
 /bin/
-/cfg/lru.hjson
+/cfg/lru.json
 /work/
 /work-vsim/
 /work-vlt/

target/snitch_cluster/Makefile

@@ -56,8 +56,8 @@ PERIPH_DIR        ?= $(ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral
 # (LRU) config, all targets depending on the configuration file have
 # to be rebuilt. This file is used to express this condition as a
 # prerequisite for other rules.
-DEFAULT_CFG = cfg/default.hjson
-CFG         = cfg/lru.hjson
+DEFAULT_CFG = cfg/default.json
+CFG         = cfg/lru.json
 
 # Common dependency for all RTL simulators
 $(BIN_DIR):
@@ -161,17 +161,14 @@ clean-rtl:
 $(GENERATED_DIR):
 	mkdir -p $@
 
-$(GENERATED_DIR)/snitch_cluster_wrapper.sv: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR)
-	$(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --wrapper
+CLUSTER_GEN_TPL = $(ROOT)/hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl
+LINK_LD_TPL     = $(ROOT)/hw/snitch_cluster/test/link.ld.tpl
+BOOTDATA_TPL    = $(ROOT)/hw/snitch_cluster/test/bootdata.cc.tpl
 
-$(GENERATED_DIR)/link.ld: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR)
-	$(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --linker
-
-$(GENERATED_DIR)/memories.json: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR)
-	$(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --memories
-
-$(GENERATED_DIR)/bootdata.cc: ${CFG} ${CLUSTER_GEN_PREREQ} | $(GENERATED_DIR)
-	$(CLUSTER_GEN) -c $< -o $(GENERATED_DIR) --bootdata
+# OCCAMYGEN artifacts
+$(eval $(call cluster_gen_rule,$(GENERATED_DIR)/snitch_cluster_wrapper.sv,$(CLUSTER_GEN_TPL)))
+$(eval $(call cluster_gen_rule,$(GENERATED_DIR)/link.ld,$(LINK_LD_TPL)))
+$(eval $(call cluster_gen_rule,$(GENERATED_DIR)/bootdata.cc,$(BOOTDATA_TPL)))
 
 # REGGEN regfile
 $(PERIPH_DIR)/snitch_cluster_peripheral_reg_pkg.sv: $(PERIPH_DIR)/snitch_cluster_peripheral_reg_top.sv

target/snitch_cluster/cfg/default.hjson → target/snitch_cluster/cfg/default.json

@@ -5,8 +5,8 @@
 // Cluster configuration for a simple testbench system.
 {
     cluster: {
-        cluster_base_addr: 268435456, // 0x1000_0000
-        cluster_base_offset: 0, // 0x0
+        cluster_base_addr: 0x10000000,
+        cluster_base_offset: 0,
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
@@ -80,20 +80,19 @@
             }
         ]
     },
-    dram: {
-        // 0x8000_0000
-        address: 2147483648,
-        // 0x8000_0000
-        length: 2147483648
-    },
-    peripherals: {
-        clint: {
-            // 0xffff_0000
-            address: 4294901760,
-            // 0x0000_1000
-            length: 4096
+    external_addr_regions: [
+        {
+            name: "dram",
+            address: 0x80000000,
+            length: 0x80000000,
+            cacheable: true
         },
-    },
+        {
+            name: "clint",
+            address: 0xFFFF0000,
+            length: 0x1000
+        },
+    ],
     // Templates.
     compute_core_template: {
         isa: "rv32imafd",

target/snitch_cluster/cfg/dma_mchan.hjson → target/snitch_cluster/cfg/dma_mchan.json

@@ -5,8 +5,8 @@
 // Cluster configuration for a simple testbench system.
 {
     cluster: {
-        cluster_base_addr: 268435456, // 0x1000_0000
-        cluster_base_offset: 0, // 0x0
+        cluster_base_addr: 0x10000000,
+        cluster_base_offset: 0,
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
@@ -81,20 +81,19 @@
             }
         ]
     },
-    dram: {
-        // 0x8000_0000
-        address: 2147483648,
-        // 0x8000_0000
-        length: 2147483648
-    },
-    peripherals: {
-        clint: {
-            // 0xffff_0000
-            address: 4294901760,
-            // 0x0000_1000
-            length: 4096
+    external_addr_regions: [
+        {
+            name: "dram",
+            address: 0x80000000,
+            length: 0x80000000,
+            cacheable: true
         },
-    },
+        {
+            name: "clint",
+            address: 0xFFFF0000,
+            length: 0x1000
+        },
+    ],
     // Templates.
     compute_core_template: {
         isa: "rv32imafd",

target/snitch_cluster/cfg/fdiv.hjson → target/snitch_cluster/cfg/fdiv.json

@@ -5,8 +5,8 @@
 // Cluster configuration for a simple testbench system.
 {
     cluster: {
-        cluster_base_addr: 268435456, // 0x1000_0000
-        cluster_base_offset: 0, // 0x0
+        cluster_base_addr: 0x10000000,
+        cluster_base_offset: 0,
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
@@ -80,20 +80,19 @@
             }
         ]
     },
-    dram: {
-        // 0x8000_0000
-        address: 2147483648,
-        // 0x8000_0000
-        length: 2147483648
-    },
-    peripherals: {
-        clint: {
-            // 0xffff_0000
-            address: 4294901760,
-            // 0x0000_1000
-            length: 4096
+    external_addr_regions: [
+        {
+            name: "dram",
+            address: 0x80000000,
+            length: 0x80000000,
+            cacheable: true
         },
-    },
+        {
+            name: "clint",
+            address: 0xFFFF0000,
+            length: 0x1000
+        },
+    ],
     // Templates.
     compute_core_template: {
         isa: "rv32imafd",

target/snitch_cluster/cfg/github-ci.hjson → target/snitch_cluster/cfg/github-ci.json

@@ -5,8 +5,8 @@
 // Cluster configuration for a simple testbench system.
 {
     cluster: {
-        cluster_base_addr: 268435456, // 0x1000_0000
-        cluster_base_offset: 0, // 0x0
+        cluster_base_addr: 0x10000000,
+        cluster_base_offset: 0,
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
@@ -76,20 +76,19 @@
             }
         ]
     },
-    dram: {
-        // 0x8000_0000
-        address: 2147483648,
-        // 0x8000_0000
-        length: 2147483648
-    },
-    peripherals: {
-        clint: {
-            // 0xffff_0000
-            address: 4294901760,
-            // 0x0000_1000
-            length: 4096
+    external_addr_regions: [
+        {
+            name: "dram",
+            address: 0x80000000,
+            length: 0x80000000,
+            cacheable: true
         },
-    },
+        {
+            name: "clint",
+            address: 0xFFFF0000,
+            length: 0x1000
+        },
+    ],
     // Templates.
     compute_core_template: {
         isa: "rv32imafd",

target/snitch_cluster/cfg/omega.hjson → target/snitch_cluster/cfg/omega.json

@@ -5,16 +5,16 @@
 // Cluster configuration for a simple testbench system.
 {
     cluster: {
-        cluster_base_addr: 268435456, // 0x1000_0000
-        cluster_base_offset: 0, // 0x0
+        cluster_base_addr: 0x10000000,
+        cluster_base_offset: 0,
         cluster_base_hartid: 0,
         addr_width: 48,
         data_width: 64,
         user_width: 5, // clog2(total number of clusters)
         tcdm: {
             size: 128,
             banks: 32,
-            topology: OmegaNet
+            topology: 'OmegaNet'
         },
         cluster_periph_size: 60, // kB
         zero_mem_size: 64, // kB
@@ -81,20 +81,19 @@
             }
         ]
     },
-    dram: {
-        // 0x8000_0000
-        address: 2147483648,
-        // 0x8000_0000
-        length: 2147483648
-    },
-    peripherals: {
-        clint: {
-            // 0xffff_0000
-            address: 4294901760,
-            // 0x0000_1000
-            length: 4096
+    external_addr_regions: [
+        {
+            name: "dram",
+            address: 0x80000000,
+            length: 0x80000000,
+            cacheable: true
         },
-    },
+        {
+            name: "clint",
+            address: 0xFFFF0000,
+            length: 0x1000
+        },
+    ],
     // Templates.
     compute_core_template: {
         isa: "rv32imafd",

target/snitch_cluster/sw.mk

@@ -17,21 +17,20 @@ clean: clean-sw
 # Platform headers #
 ####################
 
-CLUSTER_GEN_HEADERS = snitch_cluster_cfg.h \
-					  snitch_cluster_addrmap.h
+TARGET_C_HDRS_DIR = $(ROOT)/target/snitch_cluster/sw/runtime/common
 
-REGGEN_HEADERS = snitch_cluster_peripheral.h
+SNITCH_CLUSTER_CFG_H        = $(TARGET_C_HDRS_DIR)/snitch_cluster_cfg.h
+SNITCH_CLUSTER_ADDRMAP_H    = $(TARGET_C_HDRS_DIR)/snitch_cluster_addrmap.h
+SNITCH_CLUSTER_PERIPHERAL_H = $(TARGET_C_HDRS_DIR)/snitch_cluster_peripheral.h
 
-TARGET_C_HDRS_DIR = $(ROOT)/target/snitch_cluster/sw/runtime/common
-TARGET_C_HDRS     = $(addprefix $(TARGET_C_HDRS_DIR)/,$(CLUSTER_GEN_HEADERS) $(REGGEN_HEADERS))
+TARGET_C_HDRS = $(SNITCH_CLUSTER_CFG_H) $(SNITCH_CLUSTER_ADDRMAP_H) $(SNITCH_CLUSTER_PERIPHERAL_H)
 
-# CLUSTERGEN headers,
-$(addprefix $(TARGET_C_HDRS_DIR)/,$(CLUSTER_GEN_HEADERS)): %.h: $(CFG) $(CLUSTER_GEN_PREREQ) %.h.tpl
-	@echo "[CLUSTERGEN] Generate $@"
-	$(CLUSTER_GEN) -c $< --outdir $(TARGET_C_HDRS_DIR) --template $@.tpl
+# CLUSTERGEN headers
+$(eval $(call cluster_gen_rule,$(SNITCH_CLUSTER_CFG_H),$(SNITCH_CLUSTER_CFG_H).tpl))
+$(eval $(call cluster_gen_rule,$(SNITCH_CLUSTER_ADDRMAP_H),$(SNITCH_CLUSTER_ADDRMAP_H).tpl))
 
 # REGGEN headers
-$(TARGET_C_HDRS_DIR)/snitch_cluster_peripheral.h: $(ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson $(REGGEN)
+$(SNITCH_CLUSTER_PERIPHERAL_H): $(ROOT)/hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson $(REGGEN)
 	$(call reggen_generate_header,$@,$<)
 
 .PHONY: clean-headers