add prefectable

fdt-parser/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "fdt-parser"
-version = "0.4.1"
+version = "0.4.2"
 authors = ["周睿 <zrufo747@outlook.com>"]
 edition = "2021"
 repository = "https://github.com/qclic/fdt-parser"

fdt-parser/src/define.rs

@@ -243,7 +243,7 @@ impl<'a> FdtRange<'a> {
     }
 }
 
-impl<'a> Debug for FdtRange<'a> {
+impl Debug for FdtRange<'_> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         f.write_str("Range {{ child_bus_address: [ ")?;
         for addr in self.child_bus_address() {

fdt-parser/src/interrupt.rs

@@ -4,7 +4,7 @@ pub struct InterruptController<'a> {
     pub node: Node<'a>,
 }
 
-impl<'a> InterruptController<'a> {
+impl InterruptController<'_> {
     pub fn interrupt_cells(&self) -> usize {
         self.node.find_property("#interrupt-cells").unwrap().u32() as _
     }

fdt-parser/src/node.rs

@@ -171,7 +171,7 @@ struct RegIter<'a> {
     prop: Property<'a>,
     ranges: Option<FdtRangeSilce<'a>>,
 }
-impl<'a> Iterator for RegIter<'a> {
+impl Iterator for RegIter<'_> {
     type Item = FdtReg;
 
     fn next(&mut self) -> Option<Self::Item> {

fdt-parser/src/pci.rs

@@ -46,6 +46,7 @@ impl Iterator for PciRangeIter<'_> {
         let low = child.next().unwrap();
 
         let ss = (hi >> 24) & 0b11;
+        let prefetchable = (hi & 1 << 30) > 0;
 
         let space = match ss {
             0b00 => PciSpace::Configuration,
@@ -62,6 +63,7 @@ impl Iterator for PciRangeIter<'_> {
             bus_address: child_bus_address,
             cpu_address,
             size,
+            prefetchable,
         })
     }
 }
@@ -80,11 +82,12 @@ pub struct PciRange {
     pub bus_address: u64,
     pub cpu_address: u64,
     pub size: u64,
+    pub prefetchable: bool,
 }
 
 impl Debug for PciRange {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        write!(f, "PciRange {{ space: {:?}, child_bus_address: {:#x}, parent_bus_address: {:#x}, size: {:#x} }}", 
-        self.space, self.bus_address, self.cpu_address, self.size)
+        write!(f, "PciRange {{ space: {:?}, child_bus_address: {:#x}, parent_bus_address: {:#x}, size: {:#x}, prefetchable: {}}}", 
+        self.space, self.bus_address, self.cpu_address, self.size, self.prefetchable)
     }
 }

fdt-parser/tests/node.rs

@@ -163,18 +163,21 @@ mod test {
                 bus_address: 0x0,
                 cpu_address: 0x50000000,
                 size: 0xf00000,
+                prefetchable: false,
             },
             PciRange {
                 space: PciSpace::Memory32,
                 bus_address: 0x58000000,
                 cpu_address: 0x58000000,
                 size: 0x28000000,
+                prefetchable: false,
             },
             PciRange {
                 space: PciSpace::Memory64,
                 bus_address: 0x1000000000,
                 cpu_address: 0x1000000000,
                 size: 0x1000000000,
+                prefetchable: false,
             },
         ];