Issue with the reverse_endianness() function

[fahadausaf]

I am trying to compile Arm LDADDB instruction to SystemVerilog. I am facing an issue with the reverse_endianness() function which is not very descriptive.

This issue only occurs when I generate and save the System Verilog code using -sv_output_dir {path to directory}. This issue does not occur when I use just -sv, -c or -type_check directive

My understanding is when we concatenate 8-bits with 120-bits, or when we concatenate the last two sets of 8-bits of a 128-bit stream, it breaks

I tried applying some patches for undefined variables and optimizing the code. Then I get another error which looks exactly the same

Here is the description of the code files used

• Decode.sail – contains the decode block
• Execute.sail – Contains the execute block
• Main.sail – Contains the testbench
• v8_base.sail – contains over 20k lines of code extracted from Arm original v8_base library. It contains the chain of functions which is required to run LDADDB instruction.

decode.txt
execute.txt
main.txt

[fahadausaf]

The same issue arises when I tried to convert STR(register) instruction to SystemVerilog

[Alasdair]

Are you using the released version of Sail, or building from the current source? This case should be implemented here

sail/src/lib/smt_gen.ml

Line 928 in 153c7b6

| CT_fbits n, CT_fbits m, CT_lbits ->

so I'm not sure what's going on.

Probably you want to figure out what code path is leading to a 128-bit endianness reversal for an instruction like LDADDB, and statically remove it, because it it's probably for some weird case like 128-but PTEs for big endian Arm.