Cannot perform conversion from %vec(%bv64) to %fvec(31, %bv64)

[fahadausaf]

Instruction: LDR(Register)
Sail Compiler: 0.18

This error occurred while compiling Sail specification for Arm LDR-Register instruction to SystemVerilog. The code compiles successfully when compiled to C

[martinberger]

Which version of Arm do you transpile from?

[fahadausaf]

It's the latest version available on sail-repo, i.e. v9.4

[martinberger]

Looking at the screenshot above, it would be useful if the SV-backend would give an indication what source lines are causing the problem. @Alasdair is there a command line option that enables that behaviour? I know that the Sail compiler is good at tracking code provenance.

The line number 1606 in the screen shot is the definition of TMState but it's not clear if the error is triggered by translation of a constructor or destructor for TMState, or when an instance of that type is used.