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Support complex initial register state in prover backends #981

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bacam opened this issue Feb 12, 2025 · 2 comments
Open

Support complex initial register state in prover backends #981

bacam opened this issue Feb 12, 2025 · 2 comments
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@bacam
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bacam commented Feb 12, 2025

The RISC-V specification now has complex initialisers for some registers, e.g., menvcfg depends on whether certain extensions are enabled, which are decided by built-in functions. We should perhaps also allow initialisers that refers to registers declared earlier, although I don't know if anyone wants to use that. At the moment the Lem backend tries to obtain concrete values which doesn't work, and I need to check the Coq backend's behaviour.

@bacam bacam self-assigned this Feb 12, 2025
bacam added a commit to bacam/sail that referenced this issue Feb 12, 2025
bacam added a commit to bacam/sail that referenced this issue Feb 12, 2025
bacam added a commit that referenced this issue Feb 12, 2025
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bacam commented Feb 28, 2025

See #1090, which adds a new function for initialisation for Coq. I might need to tweak it a bit to allow the use of earlier registers.

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bacam commented Mar 3, 2025

A test for register initialisation order:

default Order dec
$include <prelude.sail>

val get_b : unit -> bits(16)

register c : bits(16) = get_b() + 0x0100
register a : bits(16) = 0x0001
register b : bits(16) = a + 0x0010

function get_b() -> bits(16) = b

function main() -> unit = print_bits("c ", c)

We'll probably ban expressions with effects in register initialisers.

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