Skip to content

Commit b56a585

Browse files
Aart KleinendorstAart Kleinendorst
Aart Kleinendorst
authored and
Aart Kleinendorst
committed
LPCCSE-267-da1459x-spi-read-write-example-lsm6dsl
1 parent 0ca7166 commit b56a585

File tree

14 files changed

+1419
-0
lines changed

14 files changed

+1419
-0
lines changed

interfaces/spi_write_read_example/.cproject

Lines changed: 361 additions & 0 deletions
Large diffs are not rendered by default.
Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
jlink.log
2+
.settings
3+
DA1459x-00-Debug_RAM
4+
DA1459x-00-Debug_eFlash
5+
/DA1459x-00-Release_eFLASH/
6+
/DA1459x-00-Debug_eFLASH/
Lines changed: 105 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,105 @@
1+
<?xml version="1.0" encoding="UTF-8"?>
2+
<projectDescription>
3+
<name>spi_write_read_example</name>
4+
<comment></comment>
5+
<projects>
6+
</projects>
7+
<buildSpec>
8+
<buildCommand>
9+
<name>com.renesas.cdt.dialogsdk.dialogsdkBuilder</name>
10+
<arguments>
11+
</arguments>
12+
</buildCommand>
13+
<buildCommand>
14+
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
15+
<triggers>clean,full,incremental,</triggers>
16+
<arguments>
17+
</arguments>
18+
</buildCommand>
19+
<buildCommand>
20+
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
21+
<triggers>full,incremental,</triggers>
22+
<arguments>
23+
</arguments>
24+
</buildCommand>
25+
</buildSpec>
26+
<natures>
27+
<nature>org.eclipse.cdt.core.cnature</nature>
28+
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
29+
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
30+
<nature>com.renesas.cdt.dialogsdk.dialogsdkNature</nature>
31+
</natures>
32+
<linkedResources>
33+
<link>
34+
<name>sdk</name>
35+
<type>2</type>
36+
<locationURI>virtual:/virtual</locationURI>
37+
</link>
38+
<link>
39+
<name>startup</name>
40+
<type>2</type>
41+
<locationURI>SDKROOT/sdk/bsp/startup</locationURI>
42+
</link>
43+
<link>
44+
<name>sdk/FreeRTOS</name>
45+
<type>2</type>
46+
<locationURI>SDKROOT/sdk/free_rtos</locationURI>
47+
</link>
48+
<link>
49+
<name>sdk/adapters</name>
50+
<type>2</type>
51+
<locationURI>SDKROOT/sdk/middleware/adapters</locationURI>
52+
</link>
53+
<link>
54+
<name>sdk/bsp_include</name>
55+
<type>2</type>
56+
<locationURI>SDKROOT/sdk/bsp/include</locationURI>
57+
</link>
58+
<link>
59+
<name>sdk/config</name>
60+
<type>2</type>
61+
<locationURI>SDKROOT/sdk/bsp/config</locationURI>
62+
</link>
63+
<link>
64+
<name>sdk/ldscripts</name>
65+
<type>2</type>
66+
<locationURI>SDKROOT/sdk/bsp/ldscripts/non_ble_projects</locationURI>
67+
</link>
68+
<link>
69+
<name>sdk/memory</name>
70+
<type>2</type>
71+
<locationURI>SDKROOT/sdk/bsp/memory</locationURI>
72+
</link>
73+
<link>
74+
<name>sdk/middleware_config</name>
75+
<type>2</type>
76+
<locationURI>SDKROOT/sdk/middleware/config</locationURI>
77+
</link>
78+
<link>
79+
<name>sdk/osal</name>
80+
<type>2</type>
81+
<locationURI>SDKROOT/sdk/middleware/osal</locationURI>
82+
</link>
83+
<link>
84+
<name>sdk/peripherals</name>
85+
<type>2</type>
86+
<locationURI>SDKROOT/sdk/bsp/peripherals</locationURI>
87+
</link>
88+
<link>
89+
<name>sdk/sys_man</name>
90+
<type>2</type>
91+
<locationURI>SDKROOT/sdk/bsp/system/sys_man</locationURI>
92+
</link>
93+
<link>
94+
<name>sdk/util</name>
95+
<type>2</type>
96+
<locationURI>SDKROOT/sdk/bsp/util</locationURI>
97+
</link>
98+
</linkedResources>
99+
<variableList>
100+
<variable>
101+
<name>SDKROOT</name>
102+
<value>$%7BWORKSPACE_LOC%7D</value>
103+
</variable>
104+
</variableList>
105+
</projectDescription>
Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
SPI Adapter Write Read Example
2+
==============================
3+
4+
## Overview
5+
6+
This example implements a simple write and read communication scenario over
7+
the SPI interface using the SPI adapter layer. For this demonstration the LSM6DSL ClickBoard is used. For more details about this module, you can visit [this link](https://www.mikroe.com/lsm6dsl-click).
8+
9+
The SPI interface is configured in the master role while LSM6DSL is used as an SPI slave. Button K1 is configured as a Wake Up button.
10+
11+
Upon pressing the K1 button, the SPI master begins a write operation to transmit a read command for accessing the WHO_AM_I register. Following this, it initiates a read operation to retrieve the value of the WHO_AM_I register. The data that is written and subsequently read is then displayed on the UART terminal.
12+
13+
## HW and SW configuration
14+
* **Hardware configuration**
15+
16+
- This example runs on the DA14592 Bluetooth Smart SoC devices.
17+
- The DA14592 Pro Development kit is needed for this example.
18+
- Connect the Development kit to the host computer.
19+
- Make sure the right jumpers are placed on J15 and J16.
20+
21+
**UART terminal with the following settings is needed to observe the master task printouts**
22+
23+
| Setting | Value |
24+
|:------------:|:--------:|
25+
| Baudrate | 115200 |
26+
| Data bits | 8 |
27+
| Stop bits | 1 |
28+
| Parity | None |
29+
30+
**The following pin configuration is according to the ClickBoard connector provided on the DA14592 Development kit. The pins settings are located in `peripheral_setup.h`**
31+
32+
| DA14592 | LSM6DSL |
33+
|:-----------: |:------------:|
34+
| Master | Slave |
35+
| P0_00 (CS) | CS |
36+
| P0_01 (CLK) | SCK |
37+
| P0_02 (MISO) | SDO |
38+
| P0_03 (MOSI) | SDI |
39+
40+
___________________
41+
| LSM6DSL |
42+
| |
43+
| CS SCK SDO SDI |
44+
|___________________|
45+
| | | |
46+
_____________ | | | |
47+
| CS |----------------' | | |
48+
| CLK|---------------------' | |
49+
|DA14592 MISO|-------------------------' |
50+
| MOSI|------------------------------'
51+
'_____________'
52+
53+
* **Software configuration**
54+
- e²Studio 2023-10 or greater.
55+
- SDK 10.1.2.x
56+
- **SEGGER J-Link** tools should be downloaded and installed.
57+
58+
## How to run the example
59+
60+
### Initial Setup
61+
62+
- Download the source code from the Github.
63+
- Import the project into your workspace.
64+
- Compile and launch eFLASH target.
65+
- Program the eFLASH and run the example.
66+
67+
Logic analyzer trace of SPI operation:
68+
69+
<img src="assets/sniffer_log.PNG">
70+
71+
The UART will show the following output on K1 button press:
72+
73+
<img src="assets/teraterm.PNG" width="500">
74+
75+
76+
Loading
Loading
Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
/**
2+
****************************************************************************************
3+
*
4+
* @file custom_config_eflash.h
5+
*
6+
* @brief Board Support Package. User Configuration file for cached eFLASH mode.
7+
*
8+
* Copyright (C) 2020-2024 Renesas Electronics Corporation and/or its affiliates.
9+
* All rights reserved. Confidential Information.
10+
*
11+
* This software ("Software") is supplied by Renesas Electronics Corporation and/or its
12+
* affiliates ("Renesas"). Renesas grants you a personal, non-exclusive, non-transferable,
13+
* revocable, non-sub-licensable right and license to use the Software, solely if used in
14+
* or together with Renesas products. You may make copies of this Software, provided this
15+
* copyright notice and disclaimer ("Notice") is included in all such copies. Renesas
16+
* reserves the right to change or discontinue the Software at any time without notice.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS". RENESAS DISCLAIMS ALL WARRANTIES OF ANY KIND,
19+
* WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
20+
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. TO THE
21+
* MAXIMUM EXTENT PERMITTED UNDER LAW, IN NO EVENT SHALL RENESAS BE LIABLE FOR ANY DIRECT,
22+
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING FROM, OUT OF OR IN
23+
* CONNECTION WITH THE SOFTWARE, EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY OF
24+
* SUCH DAMAGES. USE OF THIS SOFTWARE MAY BE SUBJECT TO TERMS AND CONDITIONS CONTAINED IN
25+
* AN ADDITIONAL AGREEMENT BETWEEN YOU AND RENESAS. IN CASE OF CONFLICT BETWEEN THE TERMS
26+
* OF THIS NOTICE AND ANY SUCH ADDITIONAL LICENSE AGREEMENT, THE TERMS OF THE AGREEMENT
27+
* SHALL TAKE PRECEDENCE. BY CONTINUING TO USE THIS SOFTWARE, YOU AGREE TO THE TERMS OF
28+
* THIS NOTICE.IF YOU DO NOT AGREE TO THESE TERMS, YOU ARE NOT PERMITTED TO USE THIS
29+
* SOFTWARE.
30+
*
31+
****************************************************************************************
32+
*/
33+
34+
#ifndef CUSTOM_CONFIG_EFLASH_H_
35+
#define CUSTOM_CONFIG_EFLASH_H_
36+
37+
#include "bsp_definitions.h"
38+
39+
#define CONFIG_RETARGET
40+
41+
#define dg_configEXEC_MODE MODE_IS_CACHED
42+
#define dg_configCODE_LOCATION NON_VOLATILE_IS_EMBEDDED_FLASH
43+
44+
#define dg_configUSE_WDOG (1)
45+
46+
#define dg_configUSE_SW_CURSOR (1)
47+
48+
/*************************************************************************************************\
49+
* FreeRTOS specific config
50+
*/
51+
#define OS_FREERTOS /* Define this to use FreeRTOS */
52+
#define configTOTAL_HEAP_SIZE 14000 /* This is the FreeRTOS Total Heap Size */
53+
54+
/*************************************************************************************************\
55+
* Peripheral specific config
56+
*/
57+
#define dg_configRF_ENABLE_RECALIBRATION (0)
58+
#define dg_configUSE_HW_SPI (1)
59+
#define dg_configSPI_ADAPTER (1)
60+
#define dg_configFLASH_ADAPTER (0)
61+
#define dg_configNVMS_ADAPTER (0)
62+
#define dg_configNVMS_VES (0)
63+
64+
#define DBG_PRINT_ENABLE ( 1 )
65+
66+
/* Include bsp default values */
67+
#include "bsp_defaults.h"
68+
/* Include middleware default values */
69+
#include "middleware_defaults.h"
70+
71+
#endif /* CUSTOM_CONFIG_EFLASH_H_ */
Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
/**
2+
****************************************************************************************
3+
*
4+
* @file periph_setup.h
5+
*
6+
* @brief Configuration of devices connected to board
7+
*
8+
* Copyright (C) 2020-2024 Renesas Electronics Corporation and/or its affiliates.
9+
* All rights reserved. Confidential Information.
10+
*
11+
* This software ("Software") is supplied by Renesas Electronics Corporation and/or its
12+
* affiliates ("Renesas"). Renesas grants you a personal, non-exclusive, non-transferable,
13+
* revocable, non-sub-licensable right and license to use the Software, solely if used in
14+
* or together with Renesas products. You may make copies of this Software, provided this
15+
* copyright notice and disclaimer ("Notice") is included in all such copies. Renesas
16+
* reserves the right to change or discontinue the Software at any time without notice.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS". RENESAS DISCLAIMS ALL WARRANTIES OF ANY KIND,
19+
* WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
20+
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. TO THE
21+
* MAXIMUM EXTENT PERMITTED UNDER LAW, IN NO EVENT SHALL RENESAS BE LIABLE FOR ANY DIRECT,
22+
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING FROM, OUT OF OR IN
23+
* CONNECTION WITH THE SOFTWARE, EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY OF
24+
* SUCH DAMAGES. USE OF THIS SOFTWARE MAY BE SUBJECT TO TERMS AND CONDITIONS CONTAINED IN
25+
* AN ADDITIONAL AGREEMENT BETWEEN YOU AND RENESAS. IN CASE OF CONFLICT BETWEEN THE TERMS
26+
* OF THIS NOTICE AND ANY SUCH ADDITIONAL LICENSE AGREEMENT, THE TERMS OF THE AGREEMENT
27+
* SHALL TAKE PRECEDENCE. BY CONTINUING TO USE THIS SOFTWARE, YOU AGREE TO THE TERMS OF
28+
* THIS NOTICE.IF YOU DO NOT AGREE TO THESE TERMS, YOU ARE NOT PERMITTED TO USE THIS
29+
* SOFTWARE.
30+
*
31+
****************************************************************************************
32+
*/
33+
34+
#ifndef PERIPHERAL_SETUP_H_
35+
#define PERIPHERAL_SETUP_H_
36+
37+
#define LSM6DSL_DO_PORT ( HW_GPIO_PORT_0 )
38+
#define LSM6DSL_DO_PIN ( HW_GPIO_PIN_2 )
39+
40+
#define LSM6DSL_DI_PORT ( HW_GPIO_PORT_0 )
41+
#define LSM6DSL_DI_PIN ( HW_GPIO_PIN_3 )
42+
43+
#define LSM6DSL_CLK_PORT ( HW_GPIO_PORT_0 )
44+
#define LSM6DSL_CLK_PIN ( HW_GPIO_PIN_0 )
45+
46+
#define LSM6DSL_CS_PORT ( HW_GPIO_PORT_0 )
47+
#define LSM6DSL_CS_PIN ( HW_GPIO_PIN_1 )
48+
49+
#endif /* PERIPHERAL_SETUP_H_ */

0 commit comments

Comments
 (0)