Merge branch 'dev' into fix-indent

riscv-non-isa · Feb 24, 2025 · 5365f7a · 5365f7a
2 parents 3a89617 + 6220bd3
commit 5365f7a
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diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
@@ -115,9 +115,10 @@ jobs:
           curl --location https://github.com/rems-project/sail/releases/download/0.18-linux-binary/sail.tar.gz | sudo tar xvz --directory=/usr/local --strip-components=1
           git clone https://github.com/riscv/sail-riscv.git
           cd sail-riscv
-          ARCH=RV${{ matrix.xlen }} make
+          cmake -S . -B build -DCMAKE_BUILD_TYPE=RelWithDebInfo -GNinja
+          cmake --build build
           mkdir -p $GITHUB_WORKSPACE/sail
-          mv c_emulator/riscv_sim_RV${{ matrix.xlen }} $GITHUB_WORKSPACE/sail/riscv_sim_RV${{ matrix.xlen }}
+          mv build/c_emulator/riscv_sim_rv${{ matrix.xlen }}d $GITHUB_WORKSPACE/sail/riscv_sim_rv${{ matrix.xlen }}d
 
       - name: Save cached Sail
         if: steps.cache-sail-restore.outputs.cache-hit != 'true'
@@ -135,7 +136,7 @@ jobs:
       - name: Config and run riscof for RV${{ matrix.xlen }}
         run: |
           cd riscof-plugins/rv${{ matrix.xlen }}
-          riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m/ --env ../../riscv-test-suite/env
+          riscof run --config config.ini --suite ../../riscv-test-suite/rv${{ matrix.xlen }}i_m --env ../../riscv-test-suite/env
 
       #Check the existance of the riscof work folder, and add the PATH to environment variable
       - name: Check size and determine upload path
@@ -147,8 +148,8 @@ jobs:
           if [ -d "$work_folder" ]; then
             folder_size=$(du -sm "$work_folder" | cut -f1)
             echo "Folder size: ${folder_size} MB"
-            if [ "$folder_size" -gt 1000 ]; then
-              echo "Size exceeds 1 GB. Checking if report exists."
+            if [ "$folder_size" -gt 100000 ]; then
+              echo "Size exceeds 10 GB. Checking if report exists."
               if [ -f "$report_file" ]; then
                 echo "Uploading RISCOF generated report only."
                 echo "upload_path=$report_file" >> $GITHUB_ENV
@@ -173,4 +174,4 @@ jobs:
           name: riscof-artifact-rv${{ matrix.xlen }}
           path: ${{ env.upload_path }}
           compression-level: 6
-          overwrite: true
+          overwrite: true
diff --git a/README.md b/README.md
@@ -221,11 +221,10 @@ Then build the RISC-V Sail Model:
 ```bash
 $ git clone https://github.com/riscv/sail-riscv.git
 $ cd sail-riscv
-$ ARCH=RV32 make
-$ ARCH=RV64 make
+$ ./build-simulators.sh
 ```
 
-This will create a C simulator in `c_emulator/riscv_sim_RV64` and `c_emulator/riscv_sim_RV32`. You will need to add this path to your `$PATH` or create an alias to execute them from the command line.
+This will create a C simulator in `build/c_emulator/riscv_sim_rv64d` and `build/c_emulator/riscv_sim_rv32d`. You will need to add this path to your `$PATH` or create an alias to execute them from the command line.
 
 
 ## Necessary Env Files

diff --git a/coverage/header_file.yaml b/coverage/header_file.yaml
@@ -67,7 +67,7 @@ common:
  SATP64_ASID: 0x0FFFF00000000000
  SATP64_PPN: 0x00000FFFFFFFFFFF
  SATP_MODE_OFF: 0
- SATP_MODE_SV32: 1
+ SATP_MODE_SV32: 0x1
  SATP_MODE_SV39: 8
  SATP_MODE_SV48: 9
  SATP_MODE_SV57: 10
@@ -932,4 +932,17 @@ PMP_helper_Coverpoints:
  TOR_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))
  NA4_REGION_ADDRESS_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
  NA4_PRIORITY_REGION_MATCH: (rs1_val + imm_val == (pmpaddr3 << 2))
- NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
+ NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
+
+SV32_MACROS:
+ LEVEL_1_JUMP_SIZE: (0x400000 - 4)
+ LEVEL_0_JUMP_SIZE: (0x1000-4)
+ read: "RWX"
+ writ: "rx"
+ va_data_sv32: (0x91400000)
+
+PMM_MACROS:
+ PMM_MASK: 0x300000000
+ PMM_MASK_SV57: 0x200000000
+ PMM_MASK_SV48: 0x300000000
+ PMM_MASK_DISABLED: 0x000000000
diff --git a/coverage/rv32_pmp.cgf → coverage/pmp/rv32_pmp.cgf b/coverage/rv32_pmp.cgf → coverage/pmp/rv32_pmp.cgf
diff --git a/coverage/rv64_pmp.cgf → coverage/pmp/rv64_pmp.cgf b/coverage/rv64_pmp.cgf → coverage/pmp/rv64_pmp.cgf
diff --git a/coverage/sv32/rv32_vm_sv32.cgf b/coverage/sv32/rv32_vm_sv32.cgf
diff --git a/riscof-plugins/rv32/sail_cSim/env/model_test.h b/riscof-plugins/rv32/sail_cSim/env/model_test.h
@@ -1,5 +1,11 @@
 #ifndef _COMPLIANCE_MODEL_H
 #define _COMPLIANCE_MODEL_H
+#if XLEN == 64
+  #define ALIGNMENT 3
+#else
+  #define ALIGNMENT 2
+#endif
+
 
 #define RVMODEL_DATA_SECTION \
         .pushsection .tohost,"aw",@progbits;                            \
@@ -23,12 +29,13 @@ li x1, 1                ;\
 //RV_COMPLIANCE_DATA_BEGIN                                                                          
 #define RVMODEL_DATA_BEGIN		;\
 RVMODEL_DATA_SECTION			;\
-.align 4                  ;\
+.align ALIGNMENT;\
 .global begin_signature   ;\
 begin_signature:
 
 //RV_COMPLIANCE_DATA_END                                                                            
 #define RVMODEL_DATA_END                                                      \
+.align ALIGNMENT;\
 .global end_signature; end_signature:
 
 
@@ -54,4 +61,4 @@ RVMODEL_DATA_SECTION			;\
 #define RVMODEL_CLEAR_MEXT_INT
 
 
-#endif // _COMPLIANCE_MODEL_H
+#endif // _COMPLIANCE_MODEL_H
diff --git a/riscof-plugins/rv32/sail_cSim/riscof_sail_cSim.py b/riscof-plugins/rv32/sail_cSim/riscof_sail_cSim.py
@@ -36,8 +36,8 @@ def __init__(self, *args, **kwargs):
         path = config['PATH'] if 'PATH' in config else ""
 
 
-        self.sail_exe = { '32' : os.path.join(path,"riscv_sim_RV32"),
-                '64' : os.path.join(path,"riscv_sim_RV64")}
+        self.sail_exe = { '32' : os.path.join(path,"riscv_sim_rv32d"),
+                '64' : os.path.join(path,"riscv_sim_rv64d")}
         self.isa_spec = os.path.abspath(config['ispec']) if 'ispec' in config else ''
         self.platform_spec = os.path.abspath(config['pspec']) if 'ispec' in config else ''
         self.make = config['make'] if 'make' in config else 'make'

diff --git a/riscof-plugins/rv32/spike_simple/env/model_test.h b/riscof-plugins/rv32/spike_simple/env/model_test.h
@@ -33,6 +33,7 @@ li x1, 1                ;\
 
 //RV_COMPLIANCE_DATA_END
 #define RVMODEL_DATA_END                                                      \
+.align ALIGNMENT;\
   .global end_signature; end_signature:  
 
 //RVTEST_IO_INIT
@@ -57,4 +58,4 @@ li x1, 1                ;\
 #define RVMODEL_CLEAR_MEXT_INT
 
 
-#endif // _COMPLIANCE_MODEL_H
+#endif // _COMPLIANCE_MODEL_H
diff --git a/riscof-plugins/rv64/sail_cSim/riscof_sail_cSim.py b/riscof-plugins/rv64/sail_cSim/riscof_sail_cSim.py
@@ -28,8 +28,8 @@ def __init__(self, *args, **kwargs):
             raise SystemExit(1)
         self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)
         self.pluginpath = os.path.abspath(config['pluginpath'])
-        self.sail_exe = { '32' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV32"),
-                '64' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV64")}
+        self.sail_exe = { '32' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_rv32d"),
+                '64' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_rv64d")}
         self.isa_spec = os.path.abspath(config['ispec']) if 'ispec' in config else ''
         self.platform_spec = os.path.abspath(config['pspec']) if 'ispec' in config else ''
         self.make = config['make'] if 'make' in config else 'make'

diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py
@@ -717,10 +717,10 @@ def evaluate_reg_sem_f_ext(self, reg_val, flen, iflen, postfix, f_ext_vars, inxF
                    f_ext_vars['rs'+postfix+'_sgn_prefix'] = int(sgnd_bin_val[0:iflen],2)
                 else:
                    f_ext_vars['rs'+postfix+'_sgn_prefix'] = int(0x0)
-            else:
+             else:
                 bin_val =bin(reg_val &((1<<flen)-1) | ((1<<flen) - (1<<iflen)))[2:]
-            f_ext_vars['rs'+postfix+'_nan_prefix'] =  int(bin_val[0:iflen],2)
-            bin_val = bin_val[flen-iflen:]
+             f_ext_vars['rs'+postfix+'_nan_prefix'] =  int(bin_val[0:iflen],2)
+             bin_val = bin_val[flen-iflen:]
 
 
         f_ext_vars['fs'+postfix] = int(bin_val[0], 2)

diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h
@@ -1380,6 +1380,11 @@ vmem_adj_\__MODE__\()epc:
         add     T4, T4, sp              /* calc address of correct sv_area      */
         csrr    T2, CSR_XEPC            /* T4 now pts to trapping sv_area mode  */
 
+#ifdef SKIP_MEPC
+        addi T3, T3, 0
+        j adj_\__MODE__\()epc
+#endif
+
         LREG    T3, vmem_bgn_off(T4)            // see if epc is in the vmem area
         LREG    T6, vmem_seg_siz(T4)
         add     T6, T6, T3                      // construct vmem seg end
@@ -1427,6 +1432,11 @@ adj_\__MODE__\()epc_rtn:                // adj mepc so there is at least 4B of p
 
         csrr    T2, CSR_XTVAL
 
+#ifdef SKIP_MTVAL
+        addi T3, T3, 0
+        j adj_\__MODE__\()tval
+#endif
+
 chk_\__MODE__\()tval:
         andi    T5, T5, EXCPT_CAUSE_MSK // ensures shift amt will be within range
         LI(     T3, SET_REL_TVAL_MSK)   // now check if code or data (or sig) region adjustment

diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h
@@ -21,6 +21,8 @@
 #define LEVEL3 0x03
 #define LEVEL4 0x04
 
+#define ALL_F_S 0xFFFFFFFF
+
 #define sv39 0x00
 #define sv48 0x01
 #define sv57 0x02
@@ -189,14 +191,37 @@ Mend_PMP:                                    ;\
     or _PAR, _PAR, _PR                                            ;\
     SREG _PAR, 0(_TR1);                                          
 
-#define PTE_SETUP_SV32(_PAR, _PR, _TR0, _TR1, _VAR, level)  	  ;\
-    .if (level==1)                                                ;\
-        LA(_TR1, rvtest_Sroot_pg_tbl)                             ;\
-    .endif                                                        ;\
-    .if (level==0)                                                ;\
-        LA(_TR1, rvtest_slvl1_pg_tbl)                             ;\
-    .endif                                                        ;\
-    PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level)
+#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level)  	;\
+    srli _PAR, _PAR, 12                                         ;\
+    slli _PAR, _PAR, 10                                         ;\
+    or _PAR, _PAR, _PR                                          ;\
+    .if (level==1)                                              ;\
+        LA(_TR1, rvtest_Sroot_pg_tbl)                           ;\
+        LI(_TR0, ((VA>>22)&0x3FF)<<2)                           ;\
+    .endif                                                      ;\
+    .if (level==0)                                              ;\
+        LA(_TR1, rvtest_slvl1_pg_tbl)                           ;\
+        LI(_TR0, ((VA>>12)&0x3FF)<<2)                           ;\
+    .endif                                                      ;\
+    add _TR1, _TR1, _TR0                                        ;\
+    SREG _PAR, 0(_TR1);                                          
+
+// More Robust version of PTE_SETUP_32 to setup a PTE for a PA using Va
+// in a single line.
+//args: PA: Label of Physical Address, PERMS: permissions in hex
+//args: VA: Virtual Address in hex, level: Level to store at
+#define PTE_SETUP_RV32_New(PA_LBL, PERMS, VA, level)           ;\
+    LA(a0, PA_LBL)                                             ;\
+    LI(a1, PERMS)                                              ;\
+	PTE_SETUP_RV32(a0, a1, t0, t1, VA, level)                  ;\
+
+#define SAVE_AREA_SETUP(VA, PA_LBL, _REG_NAME)                  ;\
+	LI (t0, VA)                                                 ;\
+	LA (t1, PA_LBL)                                             ;\
+	sub t0, t0, t1                                              ;\
+	LREG t1, _REG_NAME##_bgn_off+0*sv_area_sz(sp)               ;\
+	add t2, t1, t0                                              ;\
+	SREG t2, _REG_NAME##_bgn_off+1*sv_area_sz(sp)               ;\
 
 #define PTE_SETUP_SV39(_PAR, _PR, _TR0, _TR1, _VAR, level)  	  ;\
     .if (level==2)                                                ;\
@@ -615,6 +640,7 @@ Mend_PMP:                                    ;\
 #define TEST_JAL_OP(tempreg, rd, imm, label, swreg, offset, adj)	;\
 5:					;\
     LA(tempreg, 2f)			;\
+    mv rd, tempreg          ;\
     jalr x0,0(tempreg)			;\
 6:  LA(tempreg, 4f)			;\
     jalr x0,0(tempreg)			;\

diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fld-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IFDC")
+RVTEST_ISA("RV32IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fld)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fld)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fldsp-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64IFDC")
+RVTEST_ISA("RV32IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fldsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fldsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_SIGBASE(x1,signature_x1_1)

diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsd-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IFDC")
+RVTEST_ISA("RV32IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*C.*);def TEST_CASE_1=True;",c.fsd)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fsd)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S b/riscv-test-suite/rv32i_m/D_Zcd/src/c.fsdsp-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IFDC,RV64IFDC")
+RVTEST_ISA("RV32IFD_Zcd")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*C.*);def TEST_CASE_1=True;",c.fsdsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*D.*Zcd.*);def TEST_CASE_1=True;",c.fsdsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x4,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flw-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flw)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flw)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.flwsp-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flwsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.flwsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x4,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fsw-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fsw)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fsw)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)

diff --git a/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S b/riscv-test-suite/rv32i_m/F_Zcf/src/c.fswsp-01.S
@@ -19,7 +19,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32IFC")
+RVTEST_ISA("RV32IF_Zcf")
 
 .section .text.init
 .globl rvtest_entry_point
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*C.*);def TEST_CASE_1=True;",c.fswsp)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*F.*Zcf.*);def TEST_CASE_1=True;",c.fswsp)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x4,test_dataset_0)