[ACT] [CTG] [ISAC] Add support for Zhinx extension

coverage/cgfs_fext/RV32Zhinx/rv32h_fadd.cgf

@@ -0,0 +1,188 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fadd_b1:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b1(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b2:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b2(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b3:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b3(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b4:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b4(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b5:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b5(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b7:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b7(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b8:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b8(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b10:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b10(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b11:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b11(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b12:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b12(flen,16, "fadd.h", 2,True)': 0
+
+fadd_b13:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fadd.h: 0
+    rs1: 
+      <<: *all_regs
+    rs2:
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b13(flen,16, "fadd.h", 2,True)': 0

coverage/cgfs_fext/RV32Zhinx/rv32h_fclass.cgf

@@ -0,0 +1,15 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fclass_b1:
+    config: 
+      - check ISA:=regex(.*I.*Zfinx.*Zhinx.*)
+    opcode: 
+      fclass.h: 0
+    rs1: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    val_comb:
+      abstract_comb:
+        'ibm_b1(flen,16, "fclass.h", 1,True)': 0
+

coverage/cgfs_fext/RV32Zhinx/rv32h_fcvt.d.h.cgf

@@ -0,0 +1,106 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fcvt.d.h_b1:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*Zfh.*)
+    mnemonics: 
+      fcvt.d.h: 0
+    rs1: 
+      <<: *all_fregs
+    rd: 
+      <<: *all_fregs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b1(flen,16, "fcvt.d.h", 1)': 0
+
+fcvt.d.h_b22:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*Zfh.*)
+    mnemonics: 
+      fcvt.d.h: 0
+    rs1: 
+      <<: *all_fregs
+    rd: 
+      <<: *all_fregs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b22(flen,16, "fcvt.d.h", 1)': 0
+
+fcvt.d.h_b23:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*Zfh.*)
+    mnemonics: 
+      fcvt.d.h: 0
+    rs1: 
+      <<: *all_fregs
+    rd: 
+      <<: *all_fregs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b23(flen,16, "fcvt.d.h", 1)': 0
+
+fcvt.d.h_b24:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*Zfh.*)
+    mnemonics: 
+      fcvt.d.h: 0
+    rs1: 
+      <<: *all_fregs
+    rd: 
+      <<: *all_fregs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b24(flen,16, "fcvt.d.h", 1)': 0
+
+fcvt.d.h_b27:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*Zfh.*)
+    mnemonics: 
+      fcvt.d.h: 0
+    rs1: 
+      <<: *all_fregs
+    rd: 
+      <<: *all_fregs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b27(flen,16, "fcvt.d.h", 1)': 0
+
+fcvt.d.h_b28:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*Zfh.*)
+    mnemonics: 
+      fcvt.d.h: 0
+    rs1: 
+      <<: *all_fregs
+    rd: 
+      <<: *all_fregs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b28(flen,16, "fcvt.d.h", 1)': 0
+
+fcvt.d.h_b29:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*Zfh.*)
+    mnemonics: 
+      fcvt.d.h: 0
+    rs1: 
+      <<: *all_fregs
+    rd: 
+      <<: *all_fregs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        'ibm_b29(flen,16, "fcvt.d.h", 1)': 0