From 81916d30439ca451a09c82f2cf6c3e64dfd0f6fa Mon Sep 17 00:00:00 2001 From: Jiewen Yao Date: Tue, 25 Feb 2025 14:26:09 +0800 Subject: [PATCH] fix image location. Signed-off-by: Jiewen Yao --- src/iommu_data_structures.adoc | 6 +++--- src/iommu_intro.adoc | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/iommu_data_structures.adoc b/src/iommu_data_structures.adoc index 9fcc1f2..0b54537 100644 --- a/src/iommu_data_structures.adoc +++ b/src/iommu_data_structures.adoc @@ -152,7 +152,7 @@ next device-directory-table. A valid leaf device-directory-table entry holds the device-context (`DC`). .Three, two and single-level device directory with extended format `DC` -image::ddt-ext.svg[width=800,height=400, align="center"] +image::images/ddt-ext.svg[width=800,height=400, align="center"] //["ditaa",shadows=false, separation=false, font=courier, fontsize: 16] //.... // +-------+-------+-------+ +-------+-------+ +-------+ @@ -176,7 +176,7 @@ image::ddt-ext.svg[width=800,height=400, align="center"] //.... .Three, two and single-level device directory with base format `DC` -image::ddt-base.svg[width=800,height=400, align="center"] +image::images/ddt-base.svg[width=800,height=400, align="center"] //["ditaa",shadows=false, separation=false, font=courier, fontsize: 16] //.... // +-------+-------+-------+ +-------+-------+ +-------+ @@ -764,7 +764,7 @@ provides the PPN of the next level process-directory-table. The leaf process-directory-table entry holds the process-context (`PC`). .Three, two and single-level process directory -image::pdt.svg[width=800,height=400] +image::images/pdt.svg[width=800,height=400] //["ditaa",shadows=false, separation=false, font=courier, fontsize: 16] //.... // +-------+-------+-------+ +-------+-------+ +-------+ diff --git a/src/iommu_intro.adoc b/src/iommu_intro.adoc index 6fcbfe2..18fe447 100644 --- a/src/iommu_intro.adoc +++ b/src/iommu_intro.adoc @@ -291,7 +291,7 @@ allowed by the page table. [[fig:device-isolation]] .Device isolation in non-virtualized OS -image::non-virt-OS.svg[width=300,height=300, align="center"] +image::images/non-virt-OS.svg[width=300,height=300, align="center"] Legacy 32-bit devices cannot access the memory above 4 GiB. The IOMMU, through its address remapping capability, offers a simple mechanism for the device to @@ -357,7 +357,7 @@ and from D2 to VM-2 associated memory. [[fig:dma-translation-direct-device-assignment]] .DMA translation to enable direct device assignment -image::hypervisor.svg[width=300,height=300, align="center"] +image::images/hypervisor.svg[width=300,height=300, align="center"] //["ditaa",shadows=false, separation=false, fontsize: 16] //.... //+----------------+ +----------------+ @@ -391,7 +391,7 @@ address, the same as supported by regular RISC-V page-based address translation. [[MSI_REDIR]] .MSI address translation to direct guest programmed MSI to IMSIC guest interrupt files -image::msi-imsic.svg[width=500,height=400, align="center"] +image::images/msi-imsic.svg[width=500,height=400, align="center"] //["ditaa",shadows=false, separation=false, font=courier, fontsize: 16] //.... // +-----------------------+ @@ -439,7 +439,7 @@ hypervisor. [[fig:iommu-for-guest-os]] .Address translation in IOMMU for Guest OS -image::guest-OS.svg[width=500,height=400, align="center"] +image::images/guest-OS.svg[width=500,height=400, align="center"] The IOMMU is configured to perform address translation using a first-stage and second-stage page table for device D1. The second-stage is typically used by @@ -519,7 +519,7 @@ The IOMMU is not invoked for outbound transactions. [[fig:example-soc-with-iommu]] .Example of IOMMUs integration in SoC. -image::placement.svg[width=800] +image::images/placement.svg[width=800] The IOMMU is invoked by the IO Bridge for address translation and protection for inbound transactions. The data associated with the inbound transactions is not @@ -591,7 +591,7 @@ generating the associated _notice_ MSI are implementation-specific. [[fig:iommu-interfaces]] .IOMMU interfaces. -image::interfaces.svg[width=800] +image::images/interfaces.svg[width=800] Similar to the RISC-V harts, physical memory attributes (PMA) and physical memory protection (PMP) checks must be completed on all inbound IO transactions