Add address range invalidation extension

src/iommu_extensions.adoc

@@ -170,3 +170,40 @@ applies to the address range determined by the `ADDR` and `S` operands.
    the VM address spaces identified by the `GSCID` operand.
 
 <<<
+
+[[ARINV]]
+=== Address Range Invalidation Extension, Version 0.1
+
+The address range invalidation extension enables specifying a range of addresses
+in an IOMMU ATC invalidation command, reducing the number of commands queued to
+the IOMMU. This facility is especially useful when superpages are employed in
+page tables.
+
+A range-size (`S`) operand is defined at bit 73 in the `IOTINVAL.VMA` and
+`IOTINVAL.GVMA` commands. The ability to set this field to 1 is enumerated by
+`capabilities.S` (bit 43) being 1.
+
+When the `GV` operand is 0, the `S` operand is ignored by the `IOTINVAL.GVMA`
+command. When the `AV` operand is not ignored and is 0, the `S` operand
+is ignored by the `IOTINVAL.VMA` and the `IOTINVAL.GVMA` commands.
+
+When the `S` operand is 1, the `ADDR` operand represents a NAPOT range encoded
+in the `ADDR` operand itself. Starting from bit position 0 of the `ADDR`
+operand, if the first bit set to 0 is at position `X`, the range size is
+`2^(X+13)` KiB.
+
+If the `S` operand is 1 and all bits of the `ADDR` operand are 1, the behavior
+is UNSPECIFIED.
+
+If the `S` operand is 1 and the most significant bit of the `ADDR` operand is 0
+while all other bits are 1, the specified address range covers the entire
+address space.
+
+[NOTE]
+====
+The NAPOT range encoding used by this extension follows the convention used by
+PCIe ATS Invalidation Requests to denote address ranges.
+
+Simpler implementations may invalidate all address-translation cache entries
+when the `S` bit is set to 1.
+====