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riscv-non-isa · May 11, 2024 · 244aee3 · 244aee3
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Showing 5 changed files with 10 additions and 2 deletions.
diff --git a/iommu_data_structures.adoc b/iommu_data_structures.adoc
@@ -376,6 +376,8 @@ that supports multiple process contexts and thus generates a valid `process_id`
 with its memory accesses. For PCIe, for example, if the request has a PASID
 then the PASID is used as the `process_id`.
 
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+
 When `PDTV` is 1, the `DPE` bit may set to 1 to enable the use of 0 as the
 default value of `process_id` for translating requests without a valid
 `process_id`. When `PDTV` is 0, the `DPE` bit is reserved for future standard

diff --git a/iommu_hw_guidelines.adoc b/iommu_hw_guidelines.adoc
@@ -46,6 +46,8 @@ indicate this condition. For AXI, for example, the completion status is provided
 by SLVERR on RRESP (Read Data channel). For PCIe, for example, the completion
 status field may be set to "Unsupported Request" (UR) or "Completer Abort" (CA).
 
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 [[RAS]]
 === Reliability, Availability, and Serviceability (RAS)
 The IOMMU may support a RAS architecture that specifies the methods for

diff --git a/iommu_in_memory_queues.adoc b/iommu_in_memory_queues.adoc
@@ -200,7 +200,7 @@ reads from IOMMU to the corresponding first-stage page tables.
 
 .`IOTINVAL.VMA` operands and operations
 [width=75%]
-[%header, cols="2,2,3,20"]
+[%header, cols="2,2,3,30"]
 |===
 |`GV`|`AV`|`PSCV`| Operation
 |0   |0   |0     | Invalidates all address-translation cache entries, including
@@ -245,7 +245,7 @@ is illegal.
 
 .`IOTINVAL.GVMA` operands and operations
 [width=75%]
-[%header, cols="2,2,20"]
+[%header, cols="2,2,30"]
 |===
 | `GV` | `AV`   | Operation
 | 0    | ignored| Invalidates information cached from any level of the

diff --git a/iommu_registers.adoc b/iommu_registers.adoc
@@ -101,6 +101,8 @@ The reset value is 0 for the following registers fields.
 * `tr_req_ctl.Go/Busy`
 * `ddtp.busy`
 
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 The reset value is 0 for the following registers.
 
 * `ipsr`

diff --git a/iommu_sw_guidelines.adoc b/iommu_sw_guidelines.adoc
@@ -310,6 +310,8 @@ the DevATC may be satisfied by the IOMMU from the IOATC, to ensure correct
 operation software must first invalidate the IOATC before sending
 invalidations to the DevATC.
 
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 ==== Caching invalid entries
 
 This specification does not allow the caching of first/second-stage PTEs whose