From 67d518537d6e8a992175834af7757e4c9fdf2f91 Mon Sep 17 00:00:00 2001
From: Ved Shanbhogue <ved@rivosinc.com>
Date: Mon, 13 Jan 2025 13:24:56 -0600
Subject: [PATCH] Add bits introduced by non-leaf and address range
 invalidation extensions

---
 src/iommu_in_memory_queues.adoc | 10 ++++++++--
 src/iommu_registers.adoc        |  8 ++++++--
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/iommu_in_memory_queues.adoc b/src/iommu_in_memory_queues.adoc
index a3a2ead..a741bb7 100644
--- a/src/iommu_in_memory_queues.adoc
+++ b/src/iommu_in_memory_queues.adoc
@@ -154,10 +154,12 @@ the command-queue. To re-enable command processing software should clear the
   {bits: 20, name: 'PSCID'},
   {bits: 1, name: 'PSCV'},
   {bits: 1, name: 'GV'},
-  {bits: 10, name: 'rsvd'},
+  {bits: 1, name: 'NL'},
+  {bits: 9, name: 'rsvd'},
   {bits: 16, name: 'GSCID'},
   {bits: 4, name: 'rsvd'},
-  {bits: 10, name: 'rsvd'},
+  {bits: 9, name: 'rsvd'},
+  {bits: 1, name: 'S'},
   {bits: 52, name: 'ADDR[63:12]'},
   {bits: 2, name: 'rsvd'},
 ], config:{lanes: 4, hspace:1024, fontsize:12}}
@@ -185,6 +187,10 @@ When `AV` is 0, the `ADDR` operand is ignored. When `PSCV` operand is 0, the
 operand specifies an invalid address, the command may or may not perform any
 invalidations.
 
+The definition of the `NL` bit is provided by the non-leaf invalidation
+extension <<NLINV>>. The definition of the `S` bit is provided by the address
+range invalidation extension <<ARINV>>.
+
 [NOTE]
 ====
 When an invalid address is specified, an implementation may either complete the
diff --git a/src/iommu_registers.adoc b/src/iommu_registers.adoc
index 986c640..c283de0 100644
--- a/src/iommu_registers.adoc
+++ b/src/iommu_registers.adoc
@@ -155,7 +155,9 @@ the IOMMU. At reset, the register shall contain the IOMMU supported features.
   {bits: 1, name: 'PD17'},
   {bits: 1, name: 'PD20'},
   {bits: 1, name: 'QOSID'},
-  {bits: 14, name: 'reserved'},
+  {bits: 1, name: 'NL'},
+  {bits: 1, name: 'S'},
+  {bits: 12, name: 'reserved'},
   {bits: 8, name: 'custom'},
 ], config:{lanes: 8, hspace:1024}}
 ....
@@ -226,7 +228,9 @@ the IOMMU. At reset, the register shall contain the IOMMU supported features.
 |39    |`PD17`     |RO        | Two level PDT with 17-bit process_id supported.
 |40    |`PD20`     |RO        | Three level PDT with 20-bit process_id supported.
 |41    |`QOSID`    |RO        | Associating QoS IDs with requests is supported.
-|55:42 | reserved  |RO        | Reserved for standard use.
+|42    |`NL`       |RO        | Non-leaf invalidation extension is supported.
+|43    |`S`        |RO        | Address range invalidation extension is supported.
+|55:44 | reserved  |RO        | Reserved for standard use.
 |63:56 |custom     |RO        | Designated for custom use.
 |===