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signal fence_w_ip only if iofence completes #367

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merged 1 commit into from
Jun 28, 2024
Merged

signal fence_w_ip only if iofence completes #367

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12 changes: 6 additions & 6 deletions iommu_ref_model/libiommu/src/iommu_command_queue.c
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Original file line number Diff line number Diff line change
Expand Up @@ -482,12 +482,6 @@ do_iofence_c(
if ( PR == 1 || PW == 1 )
iommu_to_hb_do_global_observability_sync(PR, PW);

// The wired-signaled-interrupt (WSI) bit when set to 1 causes a wired-interrupt from the command
// queue to be generated on completion of IOFENCE.C. This bit is reserved if the IOMMU supports MSI
if ( g_reg_file.cqcsr.fence_w_ip == 0 && WSI_BIT == 1 ) {
g_reg_file.cqcsr.fence_w_ip = 1;
generate_interrupt(COMMAND_QUEUE);
}
// The AV command operand indicates if ADDR[63:2] operand and DATA operands are valid.
// If AV=1, the IOMMU writes DATA to memory at a 4-byte aligned address ADDR[63:2] * 4 as
// a 4-byte store.
Expand All @@ -501,6 +495,12 @@ do_iofence_c(
return 1;
}
}
// The wired-signaled-interrupt (WSI) bit when set to 1 causes a wired-interrupt from the command
// queue to be generated on completion of IOFENCE.C. This bit is reserved if the IOMMU supports MSI
if ( g_reg_file.cqcsr.fence_w_ip == 0 && WSI_BIT == 1 ) {
g_reg_file.cqcsr.fence_w_ip = 1;
generate_interrupt(COMMAND_QUEUE);
}
return 0;
}
// Retry a pending IOFENCE if all invalidations received
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