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Remove hard-coded entry sizes and compute queue size correctly #423

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Sep 8, 2024
Merged

Remove hard-coded entry sizes and compute queue size correctly #423

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3 changes: 3 additions & 0 deletions iommu_ref_model/libiommu/include/iommu_ats.h
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,9 @@ typedef union {
};
uint64_t raw[2];
} page_rec_t;

#define PQ_ENTRY_SZ sizeof(page_rec_t)

// IOMMU generated notifications (invalidation requests and
// page group responses)
// IOMMU response to requests from the IO bridge
Expand Down
2 changes: 2 additions & 0 deletions iommu_ref_model/libiommu/include/iommu_command_queue.h
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Expand Up @@ -90,6 +90,8 @@ typedef union {
};
} command_t;

#define CQ_ENTRY_SZ sizeof(command_t)

void do_inval_ddt(uint8_t DV, uint32_t DID);
void do_inval_pdt(uint32_t DID, uint32_t PID);
void do_iotinval_vma(uint8_t GV, uint8_t AV, uint8_t PSCV, uint32_t GSCID, uint32_t PSCID, uint64_t ADDR);
Expand Down
1 change: 1 addition & 0 deletions iommu_ref_model/libiommu/include/iommu_fault.h
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Expand Up @@ -64,6 +64,7 @@ typedef union {
#define GST_ACCESS_FAULT 0x22
#define GST_DATA_CORRUPTION 0x23

#define FQ_ENTRY_SZ sizeof(fault_rec_t)

extern void report_fault(uint16_t cause, uint64_t iotval, uint64_t iotval2, uint8_t TTYP, uint8_t dtf,
uint32_t device_id, uint8_t pid_valid, uint32_t process_id, uint8_t priv_req);
Expand Down
2 changes: 1 addition & 1 deletion iommu_ref_model/libiommu/src/iommu_ats.c
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Expand Up @@ -276,7 +276,7 @@ handle_page_request(
prec.PAYLOAD = pr->PAYLOAD;
prec.reserved0= 0;
prec.reserved1= 0;
prec_addr = ((pqb * 4096) | (pqt * 16));
prec_addr = ((pqb * PAGESIZE) | (pqt * PQ_ENTRY_SZ));
status = write_memory((char *)&prec, prec_addr, 16);
if ( (status & ACCESS_FAULT) || (status & DATA_CORRUPTION) ) {
g_reg_file.pqcsr.pqmf = 1;
Expand Down
4 changes: 2 additions & 2 deletions iommu_ref_model/libiommu/src/iommu_command_queue.c
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Expand Up @@ -63,8 +63,8 @@ process_commands(
if ( g_reg_file.cqh.index == g_reg_file.cqt.index )
return;

a = g_reg_file.cqb.ppn * PAGESIZE | (g_reg_file.cqh.index * 16);
status = read_memory(a, 16, (char *)&command);
a = g_reg_file.cqb.ppn * PAGESIZE | (g_reg_file.cqh.index * CQ_ENTRY_SZ);
status = read_memory(a, CQ_ENTRY_SZ, (char *)&command);
if ( status != 0 ) {
// If command-queue access leads to a memory fault then the
// command-queue-memory-fault bit is set to 1 and the command
Expand Down
2 changes: 1 addition & 1 deletion iommu_ref_model/libiommu/src/iommu_faults.c
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Expand Up @@ -137,7 +137,7 @@ report_fault(uint16_t cause, uint64_t iotval, uint64_t iotval2, uint8_t TTYP, ui
// and all further fault records. When an error bit is in the fqcsr changes state
// from 0 to 1 or when a new fault record is produced in the fault-queue, fault
// interrupt pending (fip) bit is set in the fqcsr.
frec_addr = ((fqb * 4096) | (fqt * 32));
frec_addr = ((fqb * PAGESIZE) | (fqt * FQ_ENTRY_SZ));
status = write_memory((char *)&frec, frec_addr, 32);
if ( (status & ACCESS_FAULT) || (status & DATA_CORRUPTION) ) {
g_reg_file.fqcsr.fqmf = 1;
Expand Down
32 changes: 20 additions & 12 deletions iommu_ref_model/test/test_utils.c
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Expand Up @@ -32,6 +32,14 @@ get_free_gppn(uint64_t num_gppn, iohgatp_t iohgatp) {
next_free_gpage[iohgatp.GSCID] = free_gppn + num_gppn;
return free_gppn;
}
uint32_t
log2szm1(uint32_t n) {
uint32_t log2sz = 0;
while (n >>= 1) {
log2sz++;
}
return log2sz > 0 ? log2sz-1 : 0;
}
int8_t
enable_cq(
uint32_t nppn) {
Expand All @@ -40,7 +48,7 @@ enable_cq(

cqb.raw = 0;
cqb.ppn = get_free_ppn(nppn);
cqb.log2szm1 = 9;
cqb.log2szm1 = 31 - __builtin_clz((nppn * PAGESIZE)/CQ_ENTRY_SZ);
write_register(CQB_OFFSET, 8, cqb.raw);
do {
cqcsr.raw = read_register(CQCSR_OFFSET, 4);
Expand Down Expand Up @@ -79,7 +87,7 @@ enable_fq(

fqb.raw = 0;
fqb.ppn = get_free_ppn(nppn);
fqb.log2szm1 = 9;
fqb.log2szm1 = 31 - __builtin_clz((nppn * PAGESIZE)/FQ_ENTRY_SZ);
write_register(FQB_OFFSET, 8, fqb.raw);
do {
fqcsr.raw = read_register(FQCSR_OFFSET, 4);
Expand Down Expand Up @@ -115,8 +123,8 @@ enable_disable_pq(

if ( enable_disable == 1 ) {
pqb.raw = 0;
pqb.ppn = get_free_ppn(4);
pqb.log2szm1 = 9;
pqb.ppn = get_free_ppn(nppn);
pqb.log2szm1 = 31 - __builtin_clz((nppn * PAGESIZE)/PQ_ENTRY_SZ);
write_register(PQB_OFFSET, 8, pqb.raw);
}
do {
Expand Down Expand Up @@ -214,7 +222,7 @@ check_exp_pq_rec(uint32_t DID, uint32_t PID, uint8_t PV, uint8_t PRIV, uint8_t E
if ( read_register(PQH_OFFSET, 4) == read_register(PQT_OFFSET, 4) ) return -1;
pqh.raw = read_register(PQH_OFFSET, 4);
pqb.raw = read_register(PQB_OFFSET, 8);
read_memory(((pqb.ppn * PAGESIZE) | (pqh.index * 16)), 16, (char *)&page_rec);
read_memory(((pqb.ppn * PAGESIZE) | (pqh.index * PQ_ENTRY_SZ)), PQ_ENTRY_SZ, (char *)&page_rec);
if ( page_rec.DID != DID ) return -1;
if ( page_rec.PID != PID ) return -1;
if ( page_rec.PV != PV ) return -1;
Expand Down Expand Up @@ -245,7 +253,7 @@ check_msg_faults(
}

fqb.raw = read_register(FQB_OFFSET, 8);
read_memory(((fqb.ppn * PAGESIZE) | (fqh.index * 32)), 32, (char *)&fault_rec);
read_memory(((fqb.ppn * PAGESIZE) | (fqh.index * FQ_ENTRY_SZ)), FQ_ENTRY_SZ, (char *)&fault_rec);

// pop the fault record
fqh.index++;
Expand Down Expand Up @@ -314,7 +322,7 @@ check_rsp_and_faults(
if ( cause == 0 ) return 0;

fqb.raw = read_register(FQB_OFFSET, 8);
read_memory(((fqb.ppn * PAGESIZE) | (fqh.index * 32)), 32, (char *)&fault_rec);
read_memory(((fqb.ppn * PAGESIZE) | (fqh.index * FQ_ENTRY_SZ)), FQ_ENTRY_SZ, (char *)&fault_rec);

// pop the fault record
fqh.index++;
Expand Down Expand Up @@ -444,7 +452,7 @@ iotinval(
cmd.iotinval.addr_63_12 = address / PAGESIZE;
cqb.raw = read_register(CQB_OFFSET, 8);
cqt.raw = read_register(CQT_OFFSET, 4);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * 16)), 16);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ);
access_viol_addr = temp;
data_corruption_addr = temp1;
cqt.index++;
Expand Down Expand Up @@ -475,7 +483,7 @@ ats_command(

cqb.raw = read_register(CQB_OFFSET, 8);
cqt.raw = read_register(CQT_OFFSET, 4);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * 16)), 16);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ);
access_viol_addr = temp;
data_corruption_addr = temp1;
cqt.index++;
Expand All @@ -493,7 +501,7 @@ generic_any(
temp1 = data_corruption_addr;
cqb.raw = read_register(CQB_OFFSET, 8);
cqt.raw = read_register(CQT_OFFSET, 4);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * 16)), 16);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ);
access_viol_addr = temp;
data_corruption_addr = temp1;
cqt.index++;
Expand Down Expand Up @@ -521,7 +529,7 @@ iodir(
cmd.iodir.pid = PID;
cqb.raw = read_register(CQB_OFFSET, 8);
cqt.raw = read_register(CQT_OFFSET, 4);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * 16)), 16);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ);
access_viol_addr = temp;
data_corruption_addr = temp1;
cqt.index++;
Expand Down Expand Up @@ -551,7 +559,7 @@ iofence(
cmd.iofence.data = data;
cqb.raw = read_register(CQB_OFFSET, 8);
cqt.raw = read_register(CQT_OFFSET, 4);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * 16)), 16);
write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqt.index * CQ_ENTRY_SZ)), CQ_ENTRY_SZ);
access_viol_addr = temp;
data_corruption_addr = temp1;
cqt.index++;
Expand Down
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