Remove VL argument from vmv.x.s intrinsics examples.

Fixes part #387 Signed-off-by: Craig Topper <craig.topper@sifive.com>
riscv-non-isa · Feb 24, 2025 · 06a8dba · 06a8dba
1 parent baab9a9
commit 06a8dba
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/doc/rvv-intrinsic-spec.adoc b/doc/rvv-intrinsic-spec.adoc
@@ -243,10 +243,10 @@ Only encoding the return type will cause naming collisions for the permutation i
 
 [,c]
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-int8_t __riscv_vmv_x_s_i8m1_i8 (vint8m1_t vs2, size_t vl);
-int8_t __riscv_vmv_x_s_i8m2_i8 (vint8m2_t vs2, size_t vl);
-int8_t __riscv_vmv_x_s_i8m4_i8 (vint8m4_t vs2, size_t vl);
-int8_t __riscv_vmv_x_s_i8m8_i8 (vint8m8_t vs2, size_t vl);
+int8_t __riscv_vmv_x_s_i8m1_i8 (vint8m1_t vs2);
+int8_t __riscv_vmv_x_s_i8m2_i8 (vint8m2_t vs2);
+int8_t __riscv_vmv_x_s_i8m4_i8 (vint8m4_t vs2);
+int8_t __riscv_vmv_x_s_i8m8_i8 (vint8m8_t vs2);
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 ==== Reduction instructions