Skip to content

Commit 7828eeb

Browse files
bjdooks-sifiveavpatel
bjdooks-sifive
authored and
avpatel
committed
gpio/desginware: add Synopsys DesignWare APB GPIO support
Add a driver for the Synopsys DesignWare APB GPIO IP block found in many SoCs. Signed-off-by: Ben Dooks <ben.dooks@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
1 parent eb736a5 commit 7828eeb

File tree

4 files changed

+148
-0
lines changed

4 files changed

+148
-0
lines changed

‎lib/utils/gpio/Kconfig

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,10 @@ config FDT_GPIO
1010

1111
if FDT_GPIO
1212

13+
config FDT_GPIO_DESIGNWARE
14+
bool "DesignWare GPIO driver"
15+
default n
16+
1317
config FDT_GPIO_SIFIVE
1418
bool "SiFive GPIO FDT driver"
1519
default n

‎lib/utils/gpio/fdt_gpio_designware.c

Lines changed: 140 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,140 @@
1+
/*
2+
* SPDX-License-Identifier: BSD-2-Clause
3+
*
4+
* Copyright (c) 2022 SiFive
5+
*
6+
* GPIO driver for Synopsys DesignWare APB GPIO
7+
*
8+
* Authors:
9+
* Ben Dooks <ben.dooks@sifive.com>
10+
*/
11+
12+
#include <libfdt.h>
13+
14+
#include <sbi/riscv_io.h>
15+
#include <sbi/sbi_error.h>
16+
17+
#include <sbi_utils/fdt/fdt_helper.h>
18+
#include <sbi_utils/gpio/fdt_gpio.h>
19+
20+
#define DW_GPIO_CHIP_MAX 4 /* need 1 per bank in use */
21+
#define DW_GPIO_PINS_MAX 32
22+
23+
#define DW_GPIO_DDR 0x4
24+
#define DW_GPIO_DR 0x0
25+
#define DW_GPIO_BIT(_b) (1UL << (_b))
26+
27+
struct dw_gpio_chip {
28+
void *dr;
29+
void *ext;
30+
struct gpio_chip chip;
31+
};
32+
33+
extern struct fdt_gpio fdt_gpio_designware;
34+
35+
static unsigned int dw_gpio_chip_count;
36+
static struct dw_gpio_chip dw_gpio_chip_array[DW_GPIO_CHIP_MAX];
37+
38+
#define pin_to_chip(__p) container_of((__p)->chip, struct dw_gpio_chip, chip);
39+
40+
static int dw_gpio_direction_output(struct gpio_pin *gp, int value)
41+
{
42+
struct dw_gpio_chip *chip = pin_to_chip(gp);
43+
unsigned long v;
44+
45+
v = readl(chip->dr + DW_GPIO_DR);
46+
if (!value)
47+
v &= ~DW_GPIO_BIT(gp->offset);
48+
else
49+
v |= DW_GPIO_BIT(gp->offset);
50+
writel(v, chip->dr + DW_GPIO_DR);
51+
52+
/* the DR is output only so we can set it then the DDR to set
53+
* the data direction, to avoid glitches.
54+
*/
55+
v = readl(chip->dr + DW_GPIO_DDR);
56+
v |= DW_GPIO_BIT(gp->offset);
57+
writel(v, chip->dr + DW_GPIO_DDR);
58+
59+
return 0;
60+
}
61+
62+
static void dw_gpio_set(struct gpio_pin *gp, int value)
63+
{
64+
struct dw_gpio_chip *chip = pin_to_chip(gp);
65+
unsigned long v;
66+
67+
v = readl(chip->dr + DW_GPIO_DR);
68+
if (!value)
69+
v &= ~DW_GPIO_BIT(gp->offset);
70+
else
71+
v |= DW_GPIO_BIT(gp->offset);
72+
writel(v, chip->dr + DW_GPIO_DR);
73+
}
74+
75+
/* notes:
76+
* each sub node is a bank and has ngpios or snpns,nr-gpios and a reg property
77+
* with the compatible `snps,dw-apb-gpio-port`.
78+
* bank A is the only one with irq support but we're not using it here
79+
*/
80+
81+
static int dw_gpio_init_bank(void *fdt, int nodeoff, u32 phandle,
82+
const struct fdt_match *match)
83+
{
84+
struct dw_gpio_chip *chip;
85+
const fdt32_t *val;
86+
uint64_t addr;
87+
int rc, poff, nr_pins, bank, len;
88+
89+
if (dw_gpio_chip_count >= DW_GPIO_CHIP_MAX)
90+
return SBI_ENOSPC;
91+
92+
/* need to get parent for the address property */
93+
poff = fdt_parent_offset(fdt, nodeoff);
94+
if (poff < 0)
95+
return SBI_EINVAL;
96+
97+
rc = fdt_get_node_addr_size(fdt, poff, 0, &addr, NULL);
98+
if (rc)
99+
return rc;
100+
101+
val = fdt_getprop(fdt, nodeoff, "reg", &len);
102+
if (!val || len <= 0)
103+
return SBI_EINVAL;
104+
bank = fdt32_to_cpu(*val);
105+
106+
val = fdt_getprop(fdt, nodeoff, "snps,nr-gpios", &len);
107+
if (!val)
108+
val = fdt_getprop(fdt, nodeoff, "ngpios", &len);
109+
if (!val || len <= 0)
110+
return SBI_EINVAL;
111+
nr_pins = fdt32_to_cpu(*val);
112+
113+
chip = &dw_gpio_chip_array[dw_gpio_chip_count];
114+
115+
chip->dr = (void *)addr + (bank * 0xc);
116+
chip->ext = (void *)addr + (bank * 4) + 0x50;
117+
chip->chip.driver = &fdt_gpio_designware;
118+
chip->chip.id = phandle;
119+
chip->chip.ngpio = nr_pins;
120+
chip->chip.set = dw_gpio_set;
121+
chip->chip.direction_output = dw_gpio_direction_output;
122+
rc = gpio_chip_add(&chip->chip);
123+
if (rc)
124+
return rc;
125+
126+
dw_gpio_chip_count++;
127+
return 0;
128+
}
129+
130+
/* since we're only probed when used, match on port not main controller node */
131+
static const struct fdt_match dw_gpio_match[] = {
132+
{ .compatible = "snps,dw-apb-gpio-port" },
133+
{ },
134+
};
135+
136+
struct fdt_gpio fdt_gpio_designware = {
137+
.match_table = dw_gpio_match,
138+
.xlate = fdt_gpio_simple_xlate,
139+
.init = dw_gpio_init_bank,
140+
};

‎lib/utils/gpio/objects.mk

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,9 @@
1010
libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio.o
1111
libsbiutils-objs-$(CONFIG_FDT_GPIO) += gpio/fdt_gpio_drivers.o
1212

13+
carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_DESIGNWARE) += fdt_gpio_designware
14+
libsbiutils-objs-$(CONFIG_FDT_GPIO_DESIGNWARE) += gpio/fdt_gpio_designware.o
15+
1316
carray-fdt_gpio_drivers-$(CONFIG_FDT_GPIO_SIFIVE) += fdt_gpio_sifive
1417
libsbiutils-objs-$(CONFIG_FDT_GPIO_SIFIVE) += gpio/fdt_gpio_sifive.o
1518

‎platform/generic/configs/defconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ CONFIG_PLATFORM_SIFIVE_FU540=y
55
CONFIG_PLATFORM_SIFIVE_FU740=y
66
CONFIG_PLATFORM_STARFIVE_JH7110=y
77
CONFIG_FDT_GPIO=y
8+
CONFIG_FDT_GPIO_DESIGNWARE=y
89
CONFIG_FDT_GPIO_SIFIVE=y
910
CONFIG_FDT_GPIO_STARFIVE=y
1011
CONFIG_FDT_I2C=y

0 commit comments

Comments
 (0)