Vector Permutation Design Document #251
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core/InstArchInfo.hpp
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| COMPRESS, | ||
| WHOLE_REG_MOVE, | ||
| UNKNOWN, | ||
| NONE |
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NONE should be before UNKNOWN.
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@govardhnn your design doc is missing the critical information that I'm looking for which is "what uops are generated for each type of permutation instruction?". It would be great to include a simple example of uop generation for each type of uop generator that you plan to add. |
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From today's meeting (2nd June, 2025), the following is the link to
my slides with the initial block diagram for the vector slide instructions.
Link: Olympia: Vector Permutation Design Proposal
<https://docs.google.com/presentation/d/1JPNQCGP9xFT4H0yEiLLE2OtRa35D_gz6fdhwKsWmmy0/edit?usp=sharing>
The reference uArch for the other `vcompress` and `vgather`
that I presented today is linked below:
[Efficient Implementation of RISC-V Vector Permutation Instructions
<https://arxiv.org/abs/2505.07112>
arXiv:2505.07112 <https://arxiv.org/abs/2505.07112>] - and will be cited in
`docs/vector_permutation.adoc`
The vector permutation design document PR#251 will also soon be extended
based on today's review feedback.
Thanks,
Govardhan
…On Mon, May 19, 2025 at 9:47 PM Kathlene Magnus ***@***.***> wrote:
***@***.**** commented on this pull request.
------------------------------
In arches/isa_json/olympia_uarch_rv64v.json
<#251 (comment)>
:
> @@ -104,7 +104,7 @@
{
"mnemonic": "vcompress.vm",
"pipe": "vpermute",
- "uop_gen": "PERMUTE",
+ "uop_gen": "COMPRESS",
This file is generated by gen_uarch_rv64v_json.py so it shouldn't be
updated directly. You can modify the Python script and then run it to
generate this file.
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Sai Govardhan
InCore Semiconductors
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