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adduw_32bit.adoc

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ADD.UW

Synopsis

Add unsigned word for address generation

{cheri_cap_mode_name} Mnemonic (RV64)

add.uw cd, rs1, cs2

{cheri_int_mode_name} Mnemonic (RV64)

add.uw rd, rs1, rs2

Encoding
{reg:[
    { bits:  7, name: 0x3b, attr: ['OP'] },
    { bits:  5, name: 'cd/rd' },
    { bits:  3, name: 0x0, attr: ['rv64: ADD.UW'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'cs2/rs2' },
    { bits:  7, name: 0x04, attr: ['rv64: ADD.UW'] },
]}
{cheri_cap_mode_name} Description

Increment the address field of cs2 by the unsigned word in rs1. Clear the tag if the resulting capability is unrepresentable or cs2 is sealed.

{cheri_int_mode_name} Description

Increment rs2 by the unsigned word in rs1.

Prerequisites for {cheri_cap_mode_name}

RV64, {cheri_base_ext_name}, Zba

Prerequisites for {cheri_int_mode_name}

RV64, {cheri_default_ext_name}, Zba

{cheri_cap_mode_name} Operation

sail::execute[clause="ZBA_RTYPEUW_capmode(_, _, _, _)",part=body,unindent]

{cheri_int_mode_name} Operation

sail::execute[clause="ZBA_RTYPEUW(_, _, _, _)",part=body,unindent]