sh4adduw_32bit.adoc

SH4ADD.UW

Synopsis

Shift by 4 and add unsigned words for address generation (SH4ADD.UW)

{cheri_cap_mode_name} Mnemonic (RV64)

sh4add.uw cd, rs1, cs2

{cheri_int_mode_name} Mnemonic (RV64)

sh4add.uw rd, rs1, rs2

Encoding

{reg:[
    { bits:  7, name: 0x3b, attr: ['OP'] },
    { bits:  5, name: 'cd/rd' },
    { bits:  3, name: 0x7, attr: ['rv64: SH4ADD.UW'] },
    { bits:  5, name: 'rs1' },
    { bits:  5, name: 'cs2/rs2' },
    { bits:  7, name: 16, attr: ['rv64: SH4ADD.UW'] },
]}

{cheri_cap_mode_name} Description

Increment the address field of cs2 by the unsigned word in rs1 shifted left by 4 bit positions and write the result to cd. The tag bit of the output capability is 0 if cs2 did not have its tag set to 1, the incremented address is outside cs2 's [section_cap_representable_check] or cs2 is sealed.

malformed_shadd_clear_tag.adoc

{cheri_int_mode_name} Description

Increment rs2 by the unsigned word in rs1 shifted left by 4 bit positions and write the result to rd.

Exceptions

None

Prerequisites for {cheri_cap_mode_name}

RV64, {sh4add_ext_name}

Prerequisites for {cheri_int_mode_name}

RV64, {sh4add_ext_name}

{cheri_cap_mode_name} Operation

sail::execute[clause="ZBA_SH4ADDUW_capmode(_, _, _)",part=body,unindent]

{cheri_int_mode_name} Operation

sail::execute[clause="ZBA_SH4ADDUW(_, _, _)",part=body,unindent]