Make c.addi16sp/c.addi4spn more consistent with the RISC-V arch spec (#…

…554)
riscv · Mar 10, 2025 · 4d34770 · 4d34770
1 parent e668e35
commit 4d34770
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Showing 4 changed files with 11 additions and 11 deletions.
diff --git a/src/insns/addi16sp_16bit.adoc b/src/insns/addi16sp_16bit.adoc
@@ -7,16 +7,16 @@ Synopsis::
 Stack pointer increment in blocks of 16 (C.ADDI16SP), 16-bit encodings
 
 {cheri_cap_mode_name} Mnemonic::
-`c.addi16sp imm`
+`c.addi16sp nzimm`
 
 {cheri_cap_mode_name} Expansion::
-`cadd csp, csp, imm`
+`caddi csp, csp, nzimm`
 
 {cheri_int_mode_name} Mnemonic::
-`c.addi16sp imm`
+`c.addi16sp nzimm`
 
 {cheri_int_mode_name} Expansion::
-`add sp, sp, imm`
+`addi sp, sp, nzimm`
 
 Encoding::
 include::wavedrom/c-int-reg-immed.adoc[]

diff --git a/src/insns/addi4spn_16bit.adoc b/src/insns/addi4spn_16bit.adoc
@@ -7,16 +7,16 @@ Synopsis::
 Stack pointer increment in blocks of 4 (C.ADDI4SPN), 16-bit encoding
 
 {cheri_cap_mode_name} Mnemonic::
-`c.addi4spn cd', uimm`
+`c.addi4spn cd', nzuimm`
 
 {cheri_cap_mode_name} Expansion::
-`cadd cd', csp, uimm`
+`caddi cd', csp, nzuimm`
 
 {cheri_int_mode_name} Mnemonic::
-`c.addi4spn rd', uimm`
+`c.addi4spn rd', nzuimm`
 
 {cheri_int_mode_name} Expansion::
-`add rd', sp, uimm`
+`addi rd', sp, nzuimm`
 
 Encoding::
 include::wavedrom/c-ciw.adoc[]

diff --git a/src/insns/wavedrom/c-ciw.adoc b/src/insns/wavedrom/c-ciw.adoc
@@ -5,7 +5,7 @@
 {reg: [
   {bits: 2, name: 'op',    type: 3, attr: ['2','C0=00'],},
   {bits: 3, name: 'rd\'',  type: 5, attr: ['3','dest'],},
-  {bits: 8, name: 'nzimm', type: 5, attr: ['8','uimm[5:4|9:6|2|3]!=0']},
+  {bits: 8, name: 'imm',   type: 5, attr: ['8','nzuimm[5:4|9:6|2|3]']},
   {bits: 3, name: 'funct3',type: 5, attr: ['3','C.ADDI4SPN=000']},
 ], config: {bits: 16}}
 ....
diff --git a/src/insns/wavedrom/c-int-reg-immed.adoc b/src/insns/wavedrom/c-int-reg-immed.adoc
@@ -4,9 +4,9 @@
 ....
 {reg: [
   {bits: 2, name: 'op',                type: 3, attr: ['2','C1=01']},
-  {bits: 5, name: 'nzimm[4|6|8:7|5]',  type: 1, attr: ['5','offset[4|6|8:7|5]']},
+  {bits: 5, name: 'imm[4|6|8:7|5]',    type: 1, attr: ['5','nzimm[4|6|8:7|5]']},
   {bits: 5, name: 'rd/rs1',            type: 5, attr: ['5','2']},
-  {bits: 1, name: 'nzimm[9]',          type: 5, attr: ['1','[9]']},
+  {bits: 1, name: 'imm[9]',            type: 5, attr: ['1','nzimm[9]']},
   {bits: 3, name: 'funct3',            type: 5, attr: ['3','C.ADDI16SP=011']},
 ], config: {bits: 16}}
 ....