Added missing description of changes to the hedeleg register

Author: francislaus

src/hypervisor-integration.adoc

@@ -50,6 +50,14 @@ VU-mode as described in xref:section_cheri_disable[xrefstyle=short].
 
 The reset value is 0.
 
+[#hedeleg,reftext="hedeleg"]
+=== Hypervisor Exception Delegation Register (hedeleg)
+
+The <<hedeleg>> register operates as described in the RISC-V Privileged
+Specification. At position 28, a new bit is added to <<hedeleg>>
+when the implementation supports {cheri_base_ext_name}. This allows CHERI
+exceptions to be delegated to VS mode.
+
 [#htval,reftext="htval"]
 === Hypervisor Trap Value Register (htval)