diff --git a/src/insns/load_16bit.adoc b/src/insns/load_16bit.adoc
index 9b8a8c5d..eb06db1c 100644
--- a/src/insns/load_16bit.adoc
+++ b/src/insns/load_16bit.adoc
@@ -41,7 +41,7 @@ Prerequisites for {cheri_cap_mode_name} C.LD::
 RV64 or RV32 with Zclsd, and {c_cheri_base_ext_names}
 
 Prerequisites for {cheri_int_mode_name} C.LD::
-RV64 or RV32 and Zclsd, {c_cheri_default_ext_names}
+RV64 or RV32 with Zclsd, {c_cheri_default_ext_names}
 
 Prerequisites {cheri_cap_mode_name} C.LW::
 {c_cheri_base_ext_names}
diff --git a/src/insns/load_16bit_sprel.adoc b/src/insns/load_16bit_sprel.adoc
index 8538628f..6849b440 100644
--- a/src/insns/load_16bit_sprel.adoc
+++ b/src/insns/load_16bit_sprel.adoc
@@ -35,10 +35,10 @@ Standard stack pointer relative load instructions, authorized by the capability
 include::load_exceptions.adoc[]
 
 Prerequisites for {cheri_cap_mode_name} C.LDSP::
-RV64 or RV32 and Zclsd, and {c_cheri_base_ext_names}
+RV64 or RV32 with Zclsd, and {c_cheri_base_ext_names}
 
 Prerequisites for {cheri_int_mode_name} C.LDSP::
-RV64 or RV32 and Zclsd, and {c_cheri_default_ext_names}
+RV64 or RV32 with Zclsd, and {c_cheri_default_ext_names}
 
 Prerequisites for {cheri_cap_mode_name} C.LWSP::
 {c_cheri_base_ext_names}
diff --git a/src/insns/load_32bit.adoc b/src/insns/load_32bit.adoc
index c6395352..13fbe178 100644
--- a/src/insns/load_32bit.adoc
+++ b/src/insns/load_32bit.adoc
@@ -64,10 +64,10 @@ operation is <<ddc>>. A copy of the loaded value is written to `rd`.
 include::load_exceptions.adoc[]
 
 Prerequisites for {cheri_cap_mode_name} LD::
-RV64 or RV32 and Zilsd, {cheri_base_ext_name}
+RV64 or RV32 with Zilsd, {cheri_base_ext_name}
 
 Prerequisites for {cheri_int_mode_name} LD::
-RV64 or RV32 and Zilsd, {cheri_default_ext_name}
+RV64 or RV32 with Zilsd, {cheri_default_ext_name}
 
 Prerequisites for {cheri_cap_mode_name} LW[U], LH[U], LB[U]::
 {cheri_base_ext_name}, OR +
diff --git a/src/insns/store_16bit.adoc b/src/insns/store_16bit.adoc
index 7f76e43b..f81c75cf 100644
--- a/src/insns/store_16bit.adoc
+++ b/src/insns/store_16bit.adoc
@@ -39,10 +39,10 @@ Standard store instructions, authorized by the capability in <<ddc>>.
 include::store_exceptions.adoc[]
 
 Prerequisites for {cheri_cap_mode_name} C.SD::
-RV64 or RV32 and Zclsd, and {c_cheri_base_ext_names}
+RV64 or RV32 with Zclsd, and {c_cheri_base_ext_names}
 
 Prerequisites for {cheri_int_mode_name} C.SD::
-RV64 or RV32 and Zclsd, and {c_cheri_default_ext_names}
+RV64 or RV32 with Zclsd, and {c_cheri_default_ext_names}
 
 Prerequisites for {cheri_cap_mode_name} C.SW::
 {c_cheri_base_ext_names}
diff --git a/src/insns/store_16bit_sprel.adoc b/src/insns/store_16bit_sprel.adoc
index 67cf3219..de2ca45a 100644
--- a/src/insns/store_16bit_sprel.adoc
+++ b/src/insns/store_16bit_sprel.adoc
@@ -39,10 +39,10 @@ Standard stack pointer relative store instructions, authorized by the capability
 include::store_exceptions.adoc[]
 
 Prerequisites for {cheri_cap_mode_name} C.SDSP::
-RV64 or RV32 and Zclsd, and {c_cheri_base_ext_names}
+RV64 or RV32 with Zclsd, and {c_cheri_base_ext_names}
 
 Prerequisites for {cheri_int_mode_name} C.SDSP::
-RV64 or RV32 and Zclsd, and {c_cheri_default_ext_names}
+RV64 or RV32 with Zclsd, and {c_cheri_default_ext_names}
 
 Prerequisites for {cheri_cap_mode_name} C.SWSP::
 {c_cheri_base_ext_names}
diff --git a/src/insns/store_32bit.adoc b/src/insns/store_32bit.adoc
index 55180444..c708fbb3 100644
--- a/src/insns/store_32bit.adoc
+++ b/src/insns/store_32bit.adoc
@@ -56,10 +56,10 @@ naturally aligned to CLEN/8 is cleared.
 include::store_exceptions.adoc[]
 
 Prerequisites for {cheri_cap_mode_name} SD::
-RV64 or RV32 and Zilsd, {cheri_base_ext_name}
+RV64 or RV32 with Zilsd, {cheri_base_ext_name}
 
 Prerequisites for {cheri_int_mode_name} SD::
-RV64 or RV32 and Zilsd, {cheri_default_ext_name}
+RV64 or RV32 with Zilsd, {cheri_default_ext_name}
 
 Prerequisites for {cheri_cap_mode_name} SW, SH, SB::
 {cheri_base_ext_name}