diff --git a/src/csv/CHERI_CSR.csv b/src/csv/CHERI_CSR.csv index 9dfdc193..9d10265e 100644 --- a/src/csv/CHERI_CSR.csv +++ b/src/csv/CHERI_CSR.csv @@ -37,9 +37,6 @@ direct write if address didn't change","✔","","","","Zcmt","Jump Vector Table "dddc","0x7bc","","D","DRW","tag=0, otherwise undefined","Apply <>. Always update the CSR with <> even if the address didn't change.","Apply <> and update the CSR with the result if the address changed, direct write if address didn't change","","✔","","","{cheri_default_ext_name}, Sdext","Debug Default Data Capability (saved/restored on debug mode entry/exit)","","","","","","","","","","","","","","","","","","","","","" -"mtdc","0x74c","","M","MRW, <>","tag=0, otherwise undefined","Update the CSR using <>.","direct write","","","","","{cheri_default_ext_name}, M-mode","Machine Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","","" -"stdc","0x163","","S","SRW, <>","tag=0, otherwise undefined","Update the CSR using <>.","direct write","","","","","{cheri_default_ext_name}, S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","","" -"vstdc","0x245","","VS","HRW, <>","tag=0, otherwise undefined","Update the CSR using <>.","direct write","","","","","{cheri_default_ext_name}, H","Virtual Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","","" "ddc","0x416","","U","URW","<>","Apply <>. Always update the CSR with <> even if the address didn't change.","Apply <> and update the CSR with the result if the address changed, direct write if address didn't change","","✔","","","{cheri_default_ext_name}","User Default Data Capability","","","","","","","","","","","","","","","","","","","","","" diff --git a/src/hypervisor-integration.adoc b/src/hypervisor-integration.adoc index b99f0b17..7c3eb94e 100644 --- a/src/hypervisor-integration.adoc +++ b/src/hypervisor-integration.adoc @@ -146,22 +146,6 @@ The <> register is as defined in cite:[riscv-priv-spec]. It must additionally support the new exception code for CHERI exceptions that <> supports. -[#vstdc,reftext="vstdc"] -=== Virtual Supervisor Trap Default Capability Register (vstdc) - -The <> register is a capability width read/write register that is -VS-mode's version of supervisor register <>. This register is only -present when the implementation supports {cheri_default_ext_name}. - -{TAG_RESET_CSR} - -{REQUIRE_CRE_CSR} - -{REQUIRE_HYBRID_CSR} - -.Virtual supervisor trap default capability register -include::img/vstdcreg.edn[] - [#vstval,reftext="vstval"] === Virtual Supervisor Trap Value Register (vstval) diff --git a/src/img/mtdcreg.edn b/src/img/mtdcreg.edn deleted file mode 100644 index ba5d74da..00000000 --- a/src/img/mtdcreg.edn +++ /dev/null @@ -1,22 +0,0 @@ -[bytefield] ----- -(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 21}]) -(def row-height 40) -(def row-header-fn nil) -(def left-margin 100) -(def right-margin 100) -(def boxes-per-row 34) -(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" "" ""])}) - -(draw-box "Tag" {:span 1}) -(draw-box "" {:span 1 :borders {}}) - -(draw-box "mtdc (Metadata)" {:span 32}) - -(draw-box "" {:span 2 :borders {}}) - -(draw-box "mtdc (Address)" {:span 32}) - -(draw-box "" {:span 2 :borders {}}) -(draw-box "MXLEN" {:span 32 :borders {}}) ----- diff --git a/src/img/stdcreg.edn b/src/img/stdcreg.edn deleted file mode 100644 index 3aeff145..00000000 --- a/src/img/stdcreg.edn +++ /dev/null @@ -1,22 +0,0 @@ -[bytefield] ----- -(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 21}]) -(def row-height 40) -(def row-header-fn nil) -(def left-margin 100) -(def right-margin 100) -(def boxes-per-row 34) -(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" "" ""])}) - -(draw-box "Tag" {:span 1}) -(draw-box "" {:span 1 :borders {}}) - -(draw-box "stdc (Metadata)" {:span 32}) - -(draw-box "" {:span 2 :borders {}}) - -(draw-box "stdc (Address)" {:span 32}) - -(draw-box "" {:span 2 :borders {}}) -(draw-box "MXLEN" {:span 32 :borders {}}) ----- diff --git a/src/img/vstdcreg.edn b/src/img/vstdcreg.edn deleted file mode 100644 index e1b5180c..00000000 --- a/src/img/vstdcreg.edn +++ /dev/null @@ -1,22 +0,0 @@ -[bytefield] ----- -(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 21}]) -(def row-height 40) -(def row-header-fn nil) -(def left-margin 100) -(def right-margin 100) -(def boxes-per-row 34) -(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1" "" ""])}) - -(draw-box "Tag" {:span 1}) -(draw-box "" {:span 1 :borders {}}) - -(draw-box "vstdc (Metadata)" {:span 32}) - -(draw-box "" {:span 2 :borders {}}) - -(draw-box "vstdc (Address)" {:span 32}) - -(draw-box "" {:span 2 :borders {}}) -(draw-box "MXLEN" {:span 32 :borders {}}) ----- diff --git a/src/riscv-hybrid-integration.adoc b/src/riscv-hybrid-integration.adoc index 3bd15786..78841c9d 100644 --- a/src/riscv-hybrid-integration.adoc +++ b/src/riscv-hybrid-integration.adoc @@ -429,22 +429,6 @@ Setting the MBE, SBE, or UBE field to a value that is not the reset value of MBE disables most CHERI features and instructions, as described in xref:section_cheri_disable[xrefstyle=short], while in that privilege mode. -[#mtdc,reftext="mtdc"] -==== Machine Trap Default Capability Register (mtdc) - -The <> register is a capability width read/write register dedicated -for use by machine mode. Typically, it is used to hold a data capability to a -machine-mode hart-local context space, to load into <>. - -{TAG_RESET_CSR} - -{REQUIRE_CRE_CSR} - -{REQUIRE_HYBRID_CSR} - -.Machine-mode trap data capability register -include::img/mtdcreg.edn[] - [#mseccfg,reftext="mseccfg"] ==== Machine Security Configuration Register (mseccfg) @@ -482,22 +466,6 @@ xref:section_cheri_disable[xrefstyle=short]. The reset value is 0. -[#stdc,reftext="stdc"] -==== Supervisor Trap Default Capability Register (stdc) - -The <> register is a capability width read/write register dedicated -for use by supervisor mode. Typically, it is used to hold a data capability to -a supervisor-mode hart-local context space, to load into <>. - -{TAG_RESET_CSR} - -{REQUIRE_CRE_CSR} - -{REQUIRE_HYBRID_CSR} - -.Supervisor trap data capability register (*stdc*) -include::img/stdcreg.edn[] - [#senvcfg,reftext="senvcfg"] ==== Supervisor Environment Configuration Register (senvcfg)