diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc
index 763cebbc..dd92f561 100644
--- a/src/riscv-integration.adoc
+++ b/src/riscv-integration.adoc
@@ -329,8 +329,9 @@ two tag bits in memory.
 === Zicsr, Control and Status Register (CSR) Instructions
 
 {cheri_base_ext_name} requires that RISC-V CSRs intended to hold addresses,
-like <<mtvec>>, are now able to hold capabilities. Therefore, such registers are
-renamed and extended to CLEN+1 bits in {cheri_base_ext_name}.
+are now able to hold capabilities. Therefore, such registers are
+extended to CLEN+1 bits in {cheri_base_ext_name} and a `c` suffix is added such
+as <<mtvec>> is extended to <<mtvecc>>.
 
 Reading or writing any part of a CLEN-bit CSR may cause
 side effects. For example, the CSR's tag bit may be cleared if a new address