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Made spelling of pseudoinstruction and pseudocode consistent (#479)
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src/cap-description.adoc

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@@ -400,7 +400,7 @@ uses a floating point representation to encode the bounds relative to the
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capability address. The base and top addresses from the bounds are decoded as
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shown below.
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WARNING: #TODO: The pseudo-code below does not have a formal notation. It is
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WARNING: #TODO: The pseudocode below does not have a formal notation. It is
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simply a place-holder while the Sail implementation is unavailable. In this
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notation, / means "integer division", [] are the bit-select operators, and
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arithmetic is signed.#

src/insns/cbld_32bit.adoc

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@@ -41,7 +41,7 @@ capabilities from integer values.
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NOTE: When `cs1` is `c0` this will copy `cs2` to `cd` and clear `cd.tag`.
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However this may change in future extensions, and so software should not
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assume `cs1==0` to be a pseudo instruction for tag clearing.
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assume `cs1==0` to be a pseudoinstruction for tag clearing.
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Exceptions::
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include::require_cre.adoc[]

src/insns/csrrw_32bit.adoc

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@@ -35,7 +35,7 @@ CSRRW writes `rs1` to extended CSRs in {cheri_int_mode_name}, and reads the addr
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If `cd` is `c0` (or `rd` is `x0`), then the instruction shall not read the CSR
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and shall not cause any of the side effects that might occur on a CSR read.
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+
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The assembler pseudo-instruction to write a capability CSR in {cheri_cap_mode_name},
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The assembler pseudoinstruction to write a capability CSR in {cheri_cap_mode_name},
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`csrw csr, cs1`, is encoded as `csrrw c0, csr, cs1`.
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Access to XLEN-wide CSRs from other extensions is as specified by RISC-V.

src/insns/dret.adoc

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@@ -17,7 +17,7 @@ Description::
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<<pcc>>.
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NOTE: The <<DRET>> instruction is the recommended way to exit debug mode. However,
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it is a pseudo instruction to return that technically does not execute from the
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it is a pseudoinstruction to return that technically does not execute from the
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program buffer or memory. It currently does not require the <<pcc>> to grant
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<<asr_perm>> so it never excepts.
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