Removed incosistent sentence about a CSR index in riscv-integration chapter

Author: francislaus

src/riscv-integration.adoc

@@ -1035,8 +1035,7 @@ include::img/stvalreg.edn[]
 ==== Supervisor Trap Value Register 2 (stval2)
 
 The <<stval2>> register is an SXLEN-bit read-write register, which is added as
-part of {cheri_base_ext_name} when the implementation supports S-mode. Its CSR
-address is 0x14b.
+part of {cheri_base_ext_name} when the implementation supports S-mode.
 
 <<stval2>> is updated following the same rules as <<mtval2>> for CHERI exceptions
 which are delegated to S-mode.