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invalid address csr updates #456

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merged 6 commits into from
Dec 6, 2024
Merged

invalid address csr updates #456

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b1a705d
fix https://github.com/riscv/riscv-cheri/issues/455
tariqkurd-repo Nov 28, 2024
5738200
clarify that tag clearing is only needed if the address actually changes
tariqkurd-repo Nov 29, 2024
4b5928a
add some flexibility
tariqkurd-repo Dec 2, 2024
8924587
Update src/riscv-integration.adoc
tariqkurd-repo Dec 6, 2024
98a11f5
Update src/riscv-integration.adoc
tariqkurd-repo Dec 6, 2024
eb98561
make wording match the risc-v spec more closely
tariqkurd-repo Dec 6, 2024
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18 changes: 13 additions & 5 deletions src/riscv-integration.adoc
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Expand Up @@ -1188,17 +1188,25 @@ this section describes how invalid address handling must be supported in
{cheri_base_ext_name} when accessing CSRs, branching and jumping, and
accessing memory.

===== Accessing CSRs
===== Updating CSRs

The following procedure must be used when executing instructions, such
as <<CSRRW>>, that write a capability A to a CSR that cannot hold all invalid
addresses:
The procedure below must be used when update a CSR with a capability A, and the CSR cannot
hold all invalid addresses, under the following circumstances:

. If A's address is invalid and A does not have infinite bounds (see
* executing instructions, such as <<CSRRW>>
* hardware updates to CSRs such as storing the <<pcc>> (which becomes capability A) into
<<mepcc>>/<<sepcc>> etc. when taking an exception.

The procedure is:

. If A's address is invalid, A does not have infinite bounds (see
xref:section_cap_encoding[xrefstyle=short]), then A's tag is set to 0.
. Write the final (potentially modified) version of capability A to the CSR e.g.
<<mtvecc>>, <<mepcc>>, etc.

NOTE: When A's address is invalid and happens to match an invalid address which the CSR
can hold, then it is implementation defined whether to clear A's tag.

===== Branches and Jumps

Control transfer instructions jump or branch to a capability A which can be:
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