sqosid.bib

@electronic{PRIV,
  title = {RISC-V Instruction Set Manual, Volume II: Privileged Architecture},
  url = {https://github.com/riscv/riscv-isa-manual},
  year = {}
}
@electronic{CBQRI,
  title = {RISC-V Capacity and Bandwidth QoS Register Interface},
  url = {https://github.com/riscv-non-isa/riscv-cbqri}
}
@article{PTCAMP,
  author = {Du Bois, Kristof and Eyerman, Stijn and Eeckhout, Lieven},
  title = {Per-Thread Cycle Accounting in Multicore Processors},
  year = {2013},
  issue_date = {January 2013},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  volume = {9},
  number = {4},
  issn = {1544-3566},
  url = {https://doi.org/10.1145/2400682.2400688},
  doi = {10.1145/2400682.2400688},
  journal = {ACM Trans. Archit. Code Optim.},
  month = {jan},
  articleno = {29},
  numpages = {22},
}
@inproceedings{HERACLES,
  author = {Lo, David and Cheng, Liqun and Govindaraju, Rama and Ranganathan, Parthasarathy and Kozyrakis, Christos},
  title = {Heracles: Improving Resource Efficiency at Scale},
  year = {2015},
  isbn = {9781450334020},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/2749469.2749475},
  doi = {10.1145/2749469.2749475},
  booktitle = {Proceedings of the 42nd Annual International Symposium on Computer Architecture},
  pages = {450–462},
  numpages = {13},
  location = {Portland, Oregon},
  series = {ISCA '15}
}