Add RV32 restriction for compressed shift instructions · riscv/sail-riscv@fd21acc

Triggered via push March 25, 2024 00:46

master

Status Success

Total duration 25m 2s

Artifacts 2

compile.yml

on: push

1 notice

There are 712 tests, see "Raw output" for the full list of tests.

Produced during runtime

Name	Size
event.json Expired	2.18 KB
tests.xml Expired	2.82 KB